74LVC4T3144PWJ Nexperia

74LVC4T3144 4-bit dual supply buffer/line driver 3-state Rev. 1 14 August 2017 Product data sheet 1 General description The 74LVC4T3144 is a 4-bit, dual-supply level translating buffer with 3-state outputs. It features four data inputs (An and B4), four data outputs (YBn and YA4), and an output enable input (OE). The device is configured to translate three inputs from V to V CC(A) CC(B) and one input from V to V . OE, An and YA4 are referenced to V and YBn CC(B) CC(A) CC(A) and B4 are referenced to V . A HIGH on OE causes the outputs to assume a high- CC(B) impedance OFF-state. The device is fully specified for partial power-down applications using I . The I OFF OFF circuitry disables outputs, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either V or V are at GND CC(A) CC(B) level, all outputs are in the high-impedance OFF-state. 2 Features and benefits Wide supply voltage range: V : 1.2 V to 5.5 V CC(A) V : 1.2 V to 5.5 V CC(B) High noise immunity Complies with JEDEC standards: JESD8-11A (1.4 V to 1.6 V) JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8C (3.0 V to 3.6 V) JESD12-6 (4.5 V to 5.5 V) ESD protection: HBM JESD22-A114F Class 3A exceeds 4000 V CDM JESD22-C101E exceeds 1000 V Maximum data rates: 200 Mbps (3.3 V to 5.0 V translation) 140 Mbps (translate to 3.3 V)) 100 Mbps (translate to 2.5 V) 75 Mbps (translate to 1.8 V) 60 Mbps (translate to 1.5 V) Suspend mode Latch-up performance exceeds 100 mA per JESD 78B Class II 24 mA output drive (V = 3.0 V) CC Inputs accept voltages up to 5.5 V Low power consumption: 30 A maximum I CC I circuitry provides partial Power-down mode operation OFF Specified from -40 C to +85 C and -40 C to +125 CNexperia 74LVC4T3144 4-bit dual supply buffer/line driver 3-state 3 Ordering information Table 1.Ordering information Type number Package Temperature Name Description Version range 74LVC4T3144PW -40 C to +125 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mm 4 Functional diagram YB1 YB2 YB3 B4 V CC(B) V CC(A) OE A1 A2 A3 YA4 aaa-027040 Figure 1. Logic symbol 5 Pinning information 5.1 Pinning 74LVC4T3144 1 14 V OE CC(A) A1 2 13 V CC(B) A2 3 12 YB1 4 11 A3 YB2 YA4 5 10 YB3 GND 6 9 n.c. 7 GND 8 B4 aaa-027283 Figure 2. Pin configuration SOT402-1 (TSSOP14) 74LVC4T3144 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2017. All rights reserved. Product data sheet Rev. 1 14 August 2017 2 / 27