74LVT14DB,118

74LVT14 3.3 V hex inverter Schmitt trigger Rev. 4 28 July 2021 Product data sheet 1. General description The 74LVT14 is a hex inverter with Schmitt-trigger inputs. Bus hold data inputs eliminate the need for external pull-up resistors to define unused inputs. This device is fully specified for partial power down applications using I . The I circuitry disables the output, preventing the potentially OFF OFF damaging backflow current through the device when it is powered down. 2. Features and benefits Different positive and negative going input threshold voltages Tolerant of slow input transitions Wide supply voltage range from 2.7 to 3.6 V Overvoltage tolerant inputs to 5.5 V BiCMOS high speed and output drive Output capability: +32 mA/-20 mA High noise immunity Direct interface with TTL levels No bus current loading when output is tied to 5 V bus Power-up 3-state I circuitry provides partial Power-down mode operation OFF Latch-up protection exceeds 500 mA per JESD78 class II level A Complies with JEDEC standard JESD8C (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114E exceeds 2000 V MM JESD22-A115-A exceeds 200 V Specified from -40 C to +85 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVT14D -40 C to +85 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74LVT14PW -40 C to +85 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mm 74LVT14BQ -40 C to +85 C DHVQFN14 plastic dual in-line compatible thermal enhanced SOT762-1 very thin quad flat package no leads 14 terminals body 2.5 3 0.85 mmNexperia 74LVT14 3.3 V hex inverter Schmitt trigger 4. Functional diagram 1 2 3 4 1A 1Y 1 2 5 6 2A 2Y 3 4 3A 3Y 6 5 9 8 4A 4Y 8 9 11 10 5A 5Y 11 10 6A 6Y 13 12 13 12 A Y mna204 001aac497 mna025 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram (one inverter) 5. Pinning information 5.1. Pinning 74LVT14 1 14 1A V CC 74LVT14 1Y 2 13 6A 1A 1 14 V 2A 3 12 6Y CC 1Y 2 13 6A 4 11 2Y 5A 2A 3 12 6Y 2Y 4 11 5A 3A 5 10 5Y 3A 5 10 5Y 3Y 6 9 4A 3Y 6 9 4A GND 7 8 4Y GND 7 8 4Y aaa-028394 001aah920 Fig. 4. Pin configuration SOT108-1 (SO14) Fig. 5. Pin configuration SOT402-1 (TSSOP14) 74LVT14 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 4 28 July 2021 2 / 13