74LVTH125PW,112 Nexperia

74LVT125 74LVTH125 3.3 V quad buffer 3-state Rev. 8 18 August 2021 Product data sheet 1. General description The 74LVT125 74LVTH125 is a quad buffer/line driver with 3-state outputs controlled by the output enable inputs (nOE). A HIGH on nOE causes the outputs to assume a high impedance OFF-state. Bus hold data inputs eliminate the need for external pull-up resistors to define unused inputs. This device is fully specified for partial power down applications using I . The I circuitry disables OFF OFF the output, preventing the potentially damaging backflow current through the device when it is powered down. 2. Features and benefits Quad bus interface 3-state buffers Wide supply voltage range from 2.7 to 3.6 V BiCMOS high speed and output drive Output capability: +64 mA and -32 mA Direct interface with TTL levels Overvoltage tolerant inputs to 5.5 V Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs Live insertion and extraction permitted No bus current loading when output is tied to 5 V bus Power-up 3-state I circuitry provides partial Power-down mode operation OFF Latch-up performance exceeds 500 mA per JESD 78 Class II Level B Complies with JEDEC standard JESD8C (2.7 V to 3.6 V) ESD protection: HBM EIA/JESD22-A114-A exceeds 2000V MM EIA/JESD22-A115-A exceeds 200V Specified from -40 C to 85 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVT125D -40 C to +85 C SO14 plastic small outline package 14 leads SOT108-1 body width 3.9 mm 74LVTH125D 74LVT125PW -40 C to +85 C TSSOP14 plastic thin shrink small outline package 14 leads SOT402-1 body width 4.4 mm 74LVTH125PW 74LVT125BQ -40 C to +85 C DHVQFN14 plastic dual in-line compatible thermal enhanced SOT762-1 very thin quad flat package no leads 14 terminals 74LVTH125BQ body 2.5 3 0.85 mmNexperia 74LVT125 74LVTH125 3.3 V quad buffer 3-state 4. Functional diagram 2 1A 1Y 3 2 1 1 1OE 3 1 EN1 5 2A 2Y 6 5 4 2OE 6 4 9 3A 3Y 8 9 8 3OE 10 10 4A 4Y nA nY 12 11 12 11 4OE 13 13 nOE mna228 mna229 mna227 Fig. 1. Logic symbol Fig. 2. IEC logic symbol Fig. 3. Logic diagram (one buffer) 5. Pinning information 5.1. Pinning 74LVT125 74LVTH125 terminal 1 index area 74LVT125 74LVTH125 2 13 1A 4OE 1Y 3 12 4A 1OE 1 14 V CC 2OE 4 11 4Y 2 13 1A 4OE 2A 5 (1) 10 3OE GND 1Y 3 12 4A 2Y 6 9 3A 2OE 4 11 4Y 5 10 001aac477 2A 3OE Transparent top view 2Y 6 9 3A (1) This is not a ground pin. There is no electrical or 7 8 GND 3Y mechanical requirement to solder the pad. In case 001aac476 soldered, the solder land should remain floating or connected to GND. Fig. 4. Pin configuration SOT108-1 (SO14) and SOT402-1 (TSSOP14) Fig. 5. Pin configuration SOT762-1 (DHVQFN14) 74LVT LVTH125 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 8 18 August 2021 2 / 13 7 1 GND 1OE 3Y 8 14 V CC