HEF4020B
14-stage binary counter
Rev. 9 21 March 2016 Product data sheet
1. General description
The HEF4020B is a 14-stage binary counter with a clock input (CP), an overriding
asynchronous master reset input (MR) and twelve fully buffered outputs (Q0, and Q3 to
Q13). The counter advances on the HIGH to LOW transition of CP. A HIGH on MR clears
all counter stages and forces all outputs LOW, independent of the state of CP. Each
counter stage is a static toggle flip-flop. A feature of the device is its high speed
(typ. 35 MHz at V =15V).
DD
It operates over a recommended V power supply range of 3 V to 15 V referenced to V
DD SS
(usually ground). Unused inputs must be connected to V , V , or another input.
DD SS
2. Features and benefits
High speed operation
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from 40 C to +85 C
Complies with JEDEC standard JESD 13-B
3. Ordering information
Table 1. Ordering information
All types operate from 40 C to +85 C.
Type number Package
Name Description Version
HEF4020BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1HEF4020B
Nexperia
14-stage binary counter
4. Functional diagram
7
67(5$ &
05 &
'
4 4 4 4
DGD
Fig 1. Functional diagram
7&
3&
0 5
4
4
4
4
DGD
Fig 2. Logic symbol Fig 3. IEC Logic symbol
4 4 4 4 4 4 4
)) )) )) )) ))
7 7 7 7 7 7 7
4 4 4 4 4 4 4
05
4
4 4 4 4 4 4 4
)) )) )) )) )) ))
7 7 7 7 7 7 7
4 4 4 4 4 4 4
5'
4 4
DGD
Fig 4. Logic diagram
HEF4020B All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2017. All rights reserved
Product data sheet Rev. 9 21 March 2016 2 of 13
4 4 4 4 4
5' 5' 5' 5' 5' 5'
))
4 4 4 4
5' 5' 5' 5' 5' 5' 5'
&3
)) ))
DDG
4
4
&7
4
4
4
4
4
4
5 &7
4 4 4 4 4 4 4 4
2817*(
&3