74AHC573PW-Q100J NXP

74AHC573-Q100 74AHCT573-Q100 Octal D-type transparant latch 3-state Rev. 1 10 June 2013 Product data sheet 1. General description The 74AHC573-Q100 74AHCT573-Q100 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7A. The 74AHC573-Q100 74AHCT573-Q100 consists of eight D-type transparent latches featuring separate D-type inputs for each latch and 3-state true outputs for bus oriented applications. A latch enable input (LE) and an output enable input (OE) are common to all latches. When pin LE is HIGH, data at the Dn inputs enters the latches. In this condition the latches are transparent, i.e. a latch output will change state each time its corresponding Dn input changes. When pin LE is LOW, the latches store the information that is present at the Dn inputs, after a set-up time preceding the HIGH-to-LOW transition of LE. When pin OE is LOW, the contents of the 8 latches are available at the outputs. When pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from 40 C to +85 C and from 40 C to +125 C Balanced propagation delays All inputs have a Schmitt trigger action Common 3-state output enable input Inputs accept voltages higher than V CC Input levels: For 74AHC573-Q100: CMOS input level For 74AHCT573-Q100: TTL input level ESD protection: MIL-STD-883, method 3015 exceeds 2000V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) Multiple package optionsNexperia 74AHC573-Q100 74AHCT573-Q100 Octal D-type transparant latch 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AHC573D-Q100 40 Cto+125 C SO20 plastic small outline package 20 leads SOT163-1 body width 7.5 mm 74AHCT573D-Q100 74AHC573PW-Q100 40 Cto+125 C TSSOP20 plastic thin shrink small outline package 20 leads SOT360-1 body width 4.4 mm 74AHCT573PW-Q100 74AHC573BQ-Q100 40 Cto+125 C DHVQFN20 plastic dual in-line compatible thermal enhanced SOT764-1 very thin quad flat package no leads 20 terminals 74AHCT573BQ-Q100 body 2.5 4.5 0.85 mm 4. Functional diagram 2 D0 Q0 19 3 D1 Q1 18 4 D2 Q2 17 5 16 D3 Q3 LATCH 3-STATE 6 D4 1 to 8 OUTPUTS Q4 15 7 D5 Q5 14 8 D6 13 Q6 9 12 D7 Q7 11 LE 1 OE mna809 Fig 1. Functional diagram 74AHC AHCT573 Q100 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2017. All rights reserved Product data sheet Rev. 1 10 June 2013 2 of 19