74AHCT1G07GW,125 NXP

74AHC1G07 74AHCT1G07 Buffer with open-drain output Rev. 7 18 November 2014 Product data sheet 1. General description 74AHC1G07 and 74AHCT1G07 are high-speed Si-gate CMOS devices. They provide a non-inverting buffer. The output of these devices is open-drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions. For digital operation this device must have a pull-up resistor to establish a logic HIGH-level. The AHC device has CMOS input switching levels and supply voltage range 2 V to 5.5 V. The AHCT device has TTL input switching levels and supply voltage range 4.5 V to 5.5 V. 2. Features and benefits High noise immunity Low power dissipation SOT353-1 and SOT753 package options ESD protection: HBM JESD22-A114E: exceeds 2000 V MM JESD22-A115-A: exceeds 200 V CDM JESD22-C101C: exceeds 1000 V Specified from 40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AHC1G07GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package SOT353-1 5 leads body width 1.25 mm 74AHCT1G07GW 74AHC1G07GV 40 C to +125 C SC-74A plastic surface-mounted package 5 leads SOT753 74AHCT1G07GV74AHC1G07 74AHCT1G07 NXP Semiconductors Buffer with open-drain output 4. Marking Table 2. Marking codes 1 Type number Marking 74AHC1G07GW AS 74AHC1G07GV A07 74AHCT1G07GW CS 74AHCT1G07GV C07 1 The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram < < < QD P PQ D PQ Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram 6. Pinning information 6.1 Pinning * &+ 7 * Q F 9 *1 < Fig 4. Pin configuration 6.2 Pin description Table 3. Pin description Symbol Pin Description n.c. 1 not connected A 2 data input GND 3 ground (0 V) Y 4 data output V 5 supply voltage CC 74AHC AHCT1G07 All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2014. All rights reserved. Product data sheet Rev. 7 18 November 2014 2 of 12 D DI && +& D *1