74AUP1G09GN NXP

74AUP1G09 Low-power 2-input AND gate with open-drain Rev. 4 28 June 2012 Product data sheet 1. General description The 74AUP1G09 provides the single 2-input AND gate with an open-drain output. The output of the device is an open-drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire V range from 0.8 V to 3.6 V. CC This device ensures a very low static and dynamic power consumption across the entire V range from 0.8 V to 3.6 V. CC This device is fully specified for partial Power-down applications using I . OFF The I circuitry disables the output, preventing the damaging backflow current through OFF the device when it is powered down. 2. Features and benefits Wide supply voltage range from 0.8 V to 3.6 V High noise immunity Complies with JEDEC standards: JESD8-12 (0.8 V to 1.3 V) JESD8-11 (0.9 V to 1.65 V) JESD8-7 (1.2 V to 1.95 V) JESD8-5 (1.8 V to 2.7 V) JESD8-B (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F Class 3A exceeds 5000 V MM JESD22-A115-A exceeds 200 V CDM JESD22-C101E exceeds 1000 V Low static power consumption; I = 0.9 A (maximum) CC Latch-up performance exceeds 100 mA per JESD 78 Class II Inputs accept voltages up to 3.6 V Low noise overshoot and undershoot < 10 % of V CC I circuitry provides partial Power-down mode operation OFF Multiple package options Specified from 40 Cto+85 C and 40 Cto+125 C74AUP1G09 NXP Semiconductors Low-power 2-input AND gate with open-drain 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP1G09GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads; SOT353-1 body width 1.25 mm 74AUP1G09GM 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads; SOT886 6 terminals; body 1 1.45 0.5 mm 74AUP1G09GF 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads; SOT891 6 terminals; body 1 1 0.5 mm 74AUP1G09GN 40 C to +125 C XSON6 extremely thin small outline package; no leads; SOT1115 6 terminals; body 0.9 1.0 0.35 mm 74AUP1G09GS 40 C to +125 C XSON6 extremely thin small outline package; no leads; SOT1202 6 terminals; body 1.0 1.0 0.35 mm 74AUP1G09GX 40 C to +125 C X2SON5 X2SON5: plastic thermal enhanced extremely thin SOT1226 small outline package; no leads; 5 terminals; body 0.8 0.8 0.35 mm 4. Marking Table 2. Marking [1] Type number Marking code 74AUP1G09GW p9 74AUP1G09GM p9 74AUP1G09GF p9 74AUP1G09GN p9 74AUP1G09GS p9 74AUP1G09GX p9 [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 5. Functional diagram Y A 1 B 4 1 Y & 2 4 A 2 GND B 001aad598 001aad599 001aad600 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram 74AUP1G09 All information provided in this document is subject to legal disclaimers. NXP B.V. 2012. All rights reserved. Product data sheet Rev. 4 28 June 2012 2 of 19