Product Information

74HC03N,652

74HC03N,652 electronic component of NXP

Datasheet
Logic Gates QUAD 2-INPUT NAND GATE OC

Manufacturer: NXP
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Price (USD)

40: USD 0.6265 ea
Line Total: USD 25.06

0 - Global Stock
MOQ: 40  Multiples: 1
Pack Size: 1
Availability Price Quantity
0 - WHS 1


Ships to you between Fri. 17 May to Thu. 23 May

MOQ : 40
Multiples : 1
40 : USD 0.6265
1250 : USD 0.5791

     
Manufacturer
Product Category
RoHS - XON
Icon ROHS
Product
Logic Family
Number of Gates
Number of Input Lines
Number of Output Lines
High Level Output Current
Low Level Output Current
Propagation Delay Time
Supply Voltage - Max
Supply Voltage - Min
Minimum Operating Temperature
Maximum Operating Temperature
Mounting Style
Package / Case
Packaging
Brand
Number Of Lines In/Out
Factory Pack Quantity :
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INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT03 Quad 2-input NAND gate December 1990 Product specication File under Integrated Circuits, IC06Philips Semiconductors Product specication Quad 2-input NAND gate 74HC/HCT03 FEATURES The 74HC/HCT03 provide the 2-input NAND function. The 74HC/HCT03 have open-drain N-transistor outputs, Level shift capability which are not clamped by a diode connected to V . In CC Output capability: standard (open drain) the OFF-state, i.e. when one input is LOW, the output I category: SSI CC may be pulled to any voltage between GND and V . Omax This allows the device to be used as a LOW-to-HIGH or HIGH-to-LOW level shifter. For digital operation and GENERAL DESCRIPTION OR-tied output applications, these devices must have a The 74HC/HCT03 are high-speed Si-gate CMOS devices pull-up resistor to establish a logic HIGH level. and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. QUICK REFERENCE DATA GND = 0 V T =25 C t =t = 6 ns amb r f TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC HCT t / t propagation delay C = 15 pF R =1 k V = 5 V 8 10 ns PZL PLZ L L CC C input capacitance 3.5 3.5 pF I C power dissipation capacitance per gate notes 1, 2 and 3 4.0 4.0 pF PD Notes 1. C is used to determine the dynamic power dissipation (P in W): PD D 2 2 2 P =C V f + (C V f ) + (V /R ) duty factor LOW, where: D PD CC i L CC o O L f = input frequency in MHz i f = output frequency in MHz o V = output voltage in V O C = output load capacitance in pF L V = supply voltage in V CC R = pull-up resistor in M L 2 (C V f ) = sum of outputs L CC o 2 (V /R ) = sum of outputs O L 2. For HC the condition is V = GND to V I CC For HCT the condition is V = GND to V - 1.5 V I CC 3. The given value of C is obtained with: PD C = 0 pF and R = L L ORDERING INFORMATION See 74HC/HCT/HCU/HCMOS Logic Package Information. December 1990 2

Tariff Desc

8542.39.23 No ..Linear/analogue and peripheral integrated circuits, timers, voltage regulators, A/D and D/A converters, telecommunication and modem integrated circuits, other than board level products Free

Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
FR9
Freescale
FREESCALE SEMI
Freescale Semicon
FREESCALE SEMICONDUC
Freescale Semiconductor
Freescale Semiconductor - NXP
NXP
NXP Freescale
NXP (FREESCALE)
NXP / Freescale
NXP SEMI
NXP Semicon
NXP SEMICONDUCTOR
NXP Semiconductors
NXP USA Inc.
PH3
PHI

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