74HC58N,652

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC58 Dual AND-OR gate December 1990 Product specication File under Integrated Circuits, IC06Philips Semiconductors Product specication Dual AND-OR gate 74HC58 FEATURES Output capability: standard I category: SSI CC GENERAL DESCRIPTION The 74HC58 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. The 58 provides two sections of AND-OR gates. One section contains a 2-wide, 3-input (1A to 1F) AND-OR gate and the second section contains a 2-wide, 2-input (2A to 2D) AND-OR gate. QUICK REFERENCE DATA GND = 0 V T = 15 C t = t = 6 ns amb r f TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC t / t propagation delay C = 15 pF V = 5 V PHL PLH L CC 1n to 1Y 11 ns 2n to 2Y 9 ns C input capacitance 3.5 pF I C power dissipation capacitance per PD notes 1 and 2 18 pF gate Notes 1. C is used to determine the dynamic power dissipation (P in W): PD D 2 2 P = C V f + (C V f ) where: D PD CC i L CC o f = input frequency in MHz i f = output frequency in MHz o C = output load capacitance in pF L V = supply voltage in V CC 2 (C V f ) = sum of outputs L CC o 2. For HC the condition is V = GND to V I CC ORDERING INFORMATION See 74HC/HCT/HCU/HCMOS Logic Package Information. December 1990 2