INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT85 4-bit magnitude comparator December 1990 Product specication File under Integrated Circuits, IC06Philips Semiconductors Product specication 4-bit magnitude comparator 74HC/HCT85 FEATURES weighted (A to A and B to B ), where A and B are the 0 3 0 3 3 3 most significant bits. Serial or parallel expansion without extra gating The operation of the 85 is described in the function table, Magnitude comparison of any binary words showing all possible logic conditions. The upper part of the Output capability: standard table describes the normal operation under all conditions I category: MSI that will occur in a single device or in a series expansion CC scheme. In the upper part of the table the three outputs are mutually exclusive. In the lower part of the table, the GENERAL DESCRIPTION outputs reflect the feed forward conditions that exist in the The 74HC/HCT85 are high-speed Si-gate CMOS devices parallel expansion scheme. and are pin compatible with low power Schottky TTL For proper compare operation the expander inputs (I , A>B (LSTTL). They are specified in compliance with JEDEC I and I ) to the least significant position must be A=B A<B standard no. 7A. connected as follows: I =I = = LOW and A<B A>B The 74HC/HCT85 are 4-bit magnitude comparators that I = HIGH. A=B can be expanded to almost any length. They perform For words greater than 4-bits, units can be cascaded by comparison of two 4-bit binary, BCD or other monotonic connecting outputs Q , Q and Q to the A<B A> A=B codes and present the three possible magnitude results at corresponding inputs of the significant comparator. the outputs (Q , Q and Q ). The 4-bit inputs are A>B A=B A<B QUICK REFERENCE DATA GND = 0 V T =25 C t =t = 6 ns amb r f TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC HCT t t propagation delay C = 15 pF V =5 V PHL/ PLH L CC A , B to Q , Q 20 22 ns n n A>B A<B A , B to Q 18 20 ns n n A=B I , I , I to Q , Q 15 15 ns A<B, A=B A>B A<B A>B I to Q 11 15 ns A=B A=B C input capacitance 3.5 3.5 pF I C power dissipation capacitance per package notes 1 and 2 18 20 pF PD Notes 1. C is used to determine the dynamic power dissipation (P in W): PD D 2 2 P =C V f + (C V f ) where: D PD CC i L CC o f = input frequency in MHz i f = output frequency in MHz o 2 (C V f ) = sum of outputs L CC o C = output load capacitance in pF L V = supply voltage in V CC 2. For HC the condition is V = GND to V I CC For HCT the condition is V = GND to V - 1.5 V I CC ORDERING INFORMATION See 74HC/HCT/HCU/HCMOS Logic Package Information. December 1990 2