74HCT174N,652

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications The IC06 74HC/HCT/HCU/HCMOS Logic Package Information The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT174 Hex D-type flip-flop with reset positive-edge trigger 1998 Jul 08 Product specication Supersedes data of September 1993 File under Integrated Circuits, IC06Philips Semiconductors Product specication Hex D-type ip-op with reset positive-edge trigger 74HC/HCT174 FEATURES The 74HC/HCT174 have six edge-triggered D-type flip-flops with individual D inputs and Q outputs. The Six edge-triggered D-type flip-flops common clock (CP) and master reset (MR) inputs load and Asynchronous master reset reset (clear) all flip-flops simultaneously. Output capability: standard The register is fully edge-triggered. The state of each D I category: MSI input, one set-up time prior to the LOW-to-HIGH clock CC transition, is transferred to the corresponding output of the flip-flop. GENERAL DESCRIPTION A LOW level on the MR input forces all outputs LOW, The 74HC/HCT174 are high-speed Si-gate CMOS devices independently of clock or data inputs. and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC The device is useful for applications requiring true outputs standard no. 7A. only and clock and master reset inputs that are common to all storage elements. QUICK REFERENCE DATA GND = 0 V T =25 C t =t = 6 ns amb r f TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC HCT t / t propagation delay C = 15 pF V =5 V PHL PLH L CC CP to Q 17 18 ns n MR to Q 13 17 ns n f maximum clock frequency 99 69 MHz max C input capacitance 3.5 3.5 pF I power dissipation C notes 1 and 2 17 17 pF PD capacitance per flip-flop Notes 1. C is used to determine the dynamic power dissipation (P in W): PD D 2 2 P =C V f + (C V f ) where: D PD CC i L CC o f = input frequency in MHz i f = output frequency in MHz o 2 (C V f ) = sum of outputs L CC o C = output load capacitance in pF L V = supply voltage in V CC 2. For HC the condition is V = GND to V I CC For HCT the condition is V = GND to V - 1.5 V I CC 1998 Jul 08 2