74HCT299N NXP

74HC299 74HCT299 8-bit universal shift register 3-state Rev. 03 28 July 2008 Product data sheet 1. General description The 74HC299 74HCT299 are high-speed Si-gate CMOS devices which are pin-compatible with Low-power Schottky TTL (LSTTL) devices. They are specied in compliance with JEDEC standard no. 7A. The 74HC299 74HCT299 contain eight edge-triggered D-type ip-ops and the interstage logic necessary to perform synchronous shift-right, shift-left, parallel load and hold operations. An operation is determined by the mode select inputs S0 and S1, as shown in Table 3. Pins I/O0 to I/O7 are ip-op 3-state buffer outputs which allow them to operate as data inputs in parallel load mode. The serial outputs Q0 and Q7 are used for expansion in serial shifting of longer words. A LOW signal on the asynchronous master reset input MR overrides the Sn and clock CP inputs and resets the ip-ops. All other state changes are initiated by the rising edge of the clock pulse. Inputs can change when the clock is in either state, provided that the recommended set-up and hold times are observed. A HIGH signal on the 3-state output enable inputs OE1 or OE2 disables the 3-state buffers and the I/On outputs are set to the high-impedance OFF-state. In this condition, the shift, hold, load and reset operations still occur when preparing for a parallel load operation. The 3-state buffers are also disabled by HIGH signals on both S0 and S1. 2. Features n Multiplexed inputs/outputs provide improved bit density n Four operating modes: u Shift left u Shift right u Hold (store) u Load data n Operates with output enable or at high-impedance OFF-state (Z) n 3-state outputs drive bus lines directly n Cascadable for n-bit word lengths n ESD protection: u HBM JESD22-A114E exceeds 2000 V u MM JESD22-A115-A exceeds 200 V n Specied from - 40 C to +85 C and from - 40 C to +125 C74HC299 74HCT299 NXP Semiconductors 8-bit universal shift register 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC299 74HC299D - 40 C to +125 C SO20 plastic small outline package 20 leads body SOT163-1 width 7.5 mm 74HC299DB - 40 C to +125 C SSOP20 plastic shrink small outline package 20 leads SOT339-1 body width 5.3 mm 74HC299N - 40 C to +125 C DIP20 plastic dual in-line package 20 leads (300 mil) SOT146-1 74HC299PW - 40 C to +125 C TSSOP20 plastic thin shrink small outline package 20 leads SOT360-1 body width 4.4 mm 74HCT299 74HCT299D - 40 C to +125 C SO20 plastic small outline package 20 leads body SOT163-1 width 7.5 mm 74HCT299DB - 40 C to +125 C SSOP20 plastic shrink small outline package 20 leads SOT339-1 body width 5.3 mm 74HCT299N - 40 C to +125 C DIP20 plastic dual in-line package 20 leads (300 mil) SOT146-1 74HCT299PW - 40 C to +125 C TSSOP20 plastic thin shrink small outline package 20 leads SOT360-1 body width 4.4 mm 4. Functional diagram 119 S0 S1 DSR DSL 11 18 CP 12 8-BIT SHIFT REGISTER MR 9 Q0 Q7 8 17 OE1 2 INPUT/3-STATE OUTPUT CIRCUITRY OE2 3 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 7 13 6 14 515 4 16 001aai460 Fig 1. Functional diagram 74HC HCT299 3 NXP B.V. 2008. All rights reserved. Product data sheet Rev. 03 28 July 2008 2 of 24