74LVC38APW,118

74LVC38A Quad 2-input NAND gate; open-drain Rev. 4 4 November 2011 Product data sheet 1. General description The 74LVC38A provides four 2-input NAND functions. The outputs are open-drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications. 2. Features and benefits 5 V tolerant inputs for interfacing with 5 V logic Wide supply voltage range from 1.2 V to 5.5 V CMOS low power consumption Direct interface with TTL levels Open-drain outputs Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V JESD8-5A (2.3 V to 2.7 V JESD8-C/JESD36 (2.7 V to 3.6 V ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115B exceeds 200 V CDM JESD22-C101E exceeds 1000 V Specified from 40 Cto+85 C and 40 Cto+125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC38AD 40 Cto +125 C SO14 plastic small outline package; 14 leads; SOT108-1 body width 3.9 mm 74LVC38ADB 40 Cto +125 C SSOP14 plastic shrink small outline package; 14 leads; SOT337-1 body width 5.3 mm 74LVC38APW 40 Cto +125 C TSSOP14 plastic thin shrink small outline package; 14 leads; SOT402-1 body width 4.4 mm 74LVC38ABQ 40 Cto +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1 thin quad flat package; no leads; 14 terminals; body 2.5 3 0.85 mm74LVC38A NXP Semiconductors Quad 2-input NAND gate; open-drain 4. Functional diagram 1 & 3 2 1 1A 1Y 3 4 2 1B & 6 5 4 2A 2Y 6 5 2B 9 & 8 9 3A 10 3Y 8 10 3B 12 4A 12 4Y 11 & 11 13 4B 13 mna697 mna698 Fig 1. Logic symbol Fig 2. IEC logic symbol Y A B GND mna699 Fig 3. Logic diagram for one gate 5. Pinning information 5.1 Pinning 74LVC38A 74LVC38A terminal 1 1A 1 14 V CC index area 1B 2 13 4B 1B 2 13 4B 1Y 3 12 4A 3 12 1Y 4A 2A 4 11 4Y 2A 4 11 4Y 5 10 2B (1) 3B GND 2B 5 10 3B 2Y 6 9 3A 2Y 6 9 3A 001aad039 GND 7 8 3Y 001aad038 Transparent top view (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Fig 4. Pin configuration for SO14 and (T)SSOP14 Fig 5. Pin configuration for DHVQFN14 74LVC38A All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved. Product data sheet Rev. 4 4 November 2011 2 of 15 GND 7 1 1A 3Y 8 14 V CC