74LVCH32244AECG:5 NXP

74LVCH32244A 32-bit buffer/line driver; 5 V input/output tolerant; 3-state Rev. 3 16 December 2011 Product data sheet 1. General description The 74LVCH32244A is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 V or 5.0 V devices. In 3-state operation outputs can handle 5 V. These features allow the use of these devices as translators in a mixed 3.3 V and 5 V environment. The 74LVCH32244A is a 32-bit non-inverting buffer/line driver with 3-state outputs. The 3-state outputs are controlled by eight output enable outputs (1OE to 8OE). A HIGH on pin nOE causes the outputs to assume a high-impedance OFF-state. To ensure the high-impedance state during power-up or power-down, pin nOE should be tied to V through a pull-up resistor; the minimum value of the resistor is determined by CC the current-sinking capability of the driver. Bus hold on data inputs eliminates the need for external pull-up resistors to hold unused or floating data inputs at a valid logic level. 2. Features and benefits 5 V tolerant inputs/outputs for interfacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6 V CMOS low-power consumption MULTIBYTE flow-through standard pinout architecture Low inductance multiple power and ground pins for minimum noise and ground bounce Direct interface with TTL levels Inputs accept voltages up to 5.5 V All data inputs have bus hold Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-B exceeds 200 V CDM JESD22-C101E exceeds 1000 V Specified from 40 C to +85 C Packaged in plastic fine-pitch ball grid array package74LVCH32244A NXP Semiconductors 32-bit buffer/line driver; 5 V input/output tolerant; 3-state 3. Ordering information Table 1: Ordering information Type number Package Temperature Name Description Version range 74LVC32244AEC 40 C to +85 C LFBGA96 plastic low profile fine-pitch ball grid array package; SOT536-1 96 balls; body 13.5 5.5 1.05 mm 4. Functional diagram 1A0 1Y0 3A0 3Y0 5A0 5Y0 7A0 7Y0 A5 A2 E5 E2 J5 J2 N5 N2 1A1 3A1 3Y1 5A1 5Y1 7A1 1Y1 7Y1 A6 A1 E6 E1 J6 J1 N6 N1 1A2 3A2 3Y2 5A2 5Y2 7A2 1Y2 7Y2 B5 B2 F5 F2 K5 K2 P5 P2 1A3 1Y3 3A3 3Y3 5A3 5Y3 7A3 7Y3 B6 B1 F6 F1 K6 K1 P6 P1 1OE 3OE 5OE 7OE A3 H4 J3 T4 2A0 2Y0 4A0 4Y0 6A0 6Y0 8A0 8Y0 C5 C2 G5 G2 L5 L2 R5 R2 2A1 2Y1 4A1 4Y1 6A1 8A1 6Y1 8Y1 C6 C1 G6 G1 L6 L1 R6 R1 2A2 2Y2 4A2 4Y2 6A2 6Y2 8A2 8Y2 D5 D2 H6 H1 M5 M2 T6 T1 2A3 2Y3 4A3 4Y3 6A3 6Y3 8A3 8Y3 D6 D1 H5 H2 M6 M1 T5 T2 2OE 4OE 6OE 8OE A4 H3 J4 T3 mna472 Fig 1. Logic symbol V CC data to internal circuit input mna473 Fig 2. Bus hold circuit 74LVCH32244A All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 16 December 2011 2 of 14