74LVCH32373AEC NXP

74LVCH32373A 32-bit transparant D-type latch with 5 V tolerant inputs/outputs 3-state Rev. 4 28 January 2013 Product data sheet 1. General description The 74LVCH32373A is a 32-bit transparent D-type latch featuring separate D-type inputs for each latch and 3-state outputs for bus-oriented applications. One latch enable input (nLE) and one output enable input (nOE) are provided for each octal. Inputs can be driven from either 3.3 V or 5 V devices. The device consists of 4 sections of eight D-type transparent latches with 3-state true outputs. When input nLE is HIGH, data at the nDn inputs enter the latches. In this condition, the latches are transparent, i.e. a latch output changes each time its corresponding D-input changes. When input nLE is LOW, the latches store the information that was present at the D-inputs one set-up time preceding the HIGH-to-LOW transition of nLE. When input nOE is LOW, the contents of the eight latches are available at the outputs. When input nOE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the nOE input does not affect the state of the latches. The inputs can be driven from either 3.3 V or 5 V devices. In 3-state operation, outputs can handle 5 V. These features allow the use of these devices in a mixed 3.3 V and 5 V environment. Bus hold on data inputs eliminates the need for external pull-up resistors to hold unused inputs. 2. Features and benefits 5 V tolerant inputs/outputs for interfacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6 V CMOS low power consumption Multibyte flow-through standard pinout architecture Multiple low inductance supply pins for minimum noise and ground bounce Direct interface with TTL levels All data inputs have bus hold High impedance when V = 0 V CC Complies with JEDEC standard: JESD8-7A (1.65 V to 1.95 V) JESD8-5A (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V)74LVCH32373A NXP Semiconductors 32-bit transparant D-type latch with 5 V tolerant inputs/outputs 3-state ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-B exceeds 200 V CDM JESD22-C101E exceeds 1000 V Specified from 40 Cto+85 C and 40 Cto+125 C Packaged in plastic fine-pitch ball grid array package 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVCH32372AEC 40 Cto+125 C LFBGA96 plastic low profile fine-pitch ball grid array SOT536-1 package 96 balls body 13.5 5.5 1.05 mm 4. Functional diagram 1D0 2D0 1Q0 2Q0 DQ DQ LATCH 1 LATCH 9 LE LE LE LE 1LE 2LE 1OE 2OE to 7 other channels to 7 other channels 3D0 4D0 DQ 3Q0 DQ 4Q0 LATCH 17 LATCH 25 LE LE LE LE 3LE 4LE 3OE 4OE to 7 other channels to 7 other channels mna493 Fig 1. Logic symbol 74LVCH32373A All information provided in this document is subject to legal disclaimers. NXP B.V. 2013. All rights reserved. Product data sheet Rev. 4 28 January 2013 2 of 16