Product Information

74VHCT125BQ

74VHCT125BQ electronic component of NXP

Datasheet
Buffer/Line Driver 4-CH Non-Inverting 3-ST CMOS 14-Pin DHVQFN EP
Manufacturer: NXP
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



Price (USD)

11: USD 3.2232 ea
Line Total: USD 35.46

0 - Global Stock
MOQ: 11  Multiples: 1
Pack Size: 1

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0 - WHS 1


Ships to you between Fri. 24 May to Thu. 30 May

MOQ : 11
Multiples : 1
11 : USD 3.2232

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RoHS - XON
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Number of Input Lines
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Supply Voltage - Max
Supply Voltage - Min
High Level Output Current
Low Level Output Current
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Maximum Operating Temperature
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Additional Infomation About Product

Important notice Dear Customer, On 7 February 2017 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS semiconductors with its focus on the automotive, industrial, computing, consumer and wearable application markets In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below. Instead of 74VHC125; 74VHCT125 Quad buffer/line driver; 3-state Rev. 02 13 October 2009 Product data sheet 1. General description The 74VHC125; 74VHCT125 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specied in compliance with JEDEC standard JESD7-A. The 74VHC125; 74VHCT125 provides four non-inverting buffer/line drivers with 3-state outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE). A HIGH at nOE causes the outputs to assume a high-impedance OFF-state. The 74VHC125; 74VHCT125 are identical to the 74VHC126; 74VHCT126 but have active LOW enable inputs. 2. Features n Balanced propagation delays n All inputs have a Schmitt-trigger action n Inputs accepts voltages higher than V CC n Input levels: u The 74VHC125 operates with CMOS logic levels u The 74VHCT125 operates with TTL logic levels n ESD protection: u HBM JESD22-A114E exceeds 2000 V u MM JESD22-A115-A exceeds 200 V u CDM JESD22-C101C exceeds 1000 V n Multiple package options n Specied from - 40 C to +85 C and from - 40 C to +125 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74VHC125D - 40 C to +125 C SO14 plastic small outline package; 14 leads; SOT108-1 body width 3.9 mm 74VHCT125D 74VHC125PW - 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads; SOT402-1 body width 4.4 mm 74VHCT125PW 74VHC125BQ - 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1 thin quad at package; no leads; 14 terminals; 74VHCT125BQ body 2.5 3 0.85 mm

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