GTL2107PW,118 NXP

GTL2107 12-bit GTL /GTL/GTL+ to LVTTL translator Rev. 05 23 December 2009 Product data sheet 1. General description The GTL2107 is a customized translator between dual Xeon processors, GTL/GTL/GTL+ I/O and the Platform Health Management, South Bridge and Power Supply 3.3 V LVTTL and GTL signals. 2. Features Operates as a GTL to LVTTL sampling receiver or LVTTL to GTL driver Operates at GTL, GTL+ or GTL levels EN1 and EN2 enable control 3.0 V to 3.6 V operation LVTTL I/O not 5 V tolerant Series termination on the LVTTL outputs of 30 ESD protection exceeds 2000 V HBM per JESD22-A114, 150 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 Class II, Level A which exceeds 500 mA Package offered: TSSOP28 3. Quick reference data Table 1. Quick reference data T =25 C. amb Symbol Parameter Conditions Min Typ Max Unit V =0.73V V =1.1 V ref TT t LOW to HIGH nA to nBI see Figure 4 14 8 ns PLH propagation delay nBI to nA or nAO (open-drain outputs) see Figure 13 213 18 ns t HIGH to LOW nA to nBI see Figure 4 2 5.5 10 ns PHL propagation delay nBI to nA or nAO (open-drain outputs) see Figure 13 2 4 10 ns V =0.76V V =1.2 V ref TT t LOW to HIGH nA to nBI see Figure 4 14 8 ns PLH propagation delay nBI to nA or nAO (open-drain outputs) see Figure 13 213 18 ns t HIGH to LOW nA to nBI see Figure 4 2 5.5 10 ns PHL propagation delay nBI to nA or nAO (open-drain outputs) see Figure 13 2 4 10 nsNXP Semiconductors GTL2107 12-bit GTL /GTL/GTL+ to LVTTL translator 4. Ordering information Table 2. Ordering information T = 40 Cto +85 C. amb Type Topside Package number mark Name Description Version GTL2107PW GTL2107 TSSOP28 plastic thin shrink small outline package 28 leads body width 4.4 mm SOT361-1 5. Functional diagram GTL2107 1 GTL VREF 27 2 1BI 1AO GTL inputs LVTTL outputs (open-drain) 26 2BI 3 2AO 4 & 5A 25 7BO1 LVTTL inputs/outputs (open-drain) GTL outputs 5 & 6A 24 7BO2 6 LVTTL input EN1 23 EN2 LVTTL input 7 1 GTL input 11BI 22 11BO GTL output (1) LVTTL input/output 8 DELAY 11A (open-drain) 21 5BI 9 (1) DELAY GTL input 9BI 20 6BI GTL inputs 19 10 3BI 3AO LVTTL outputs (open-drain) 18 11 4BI 4AO 1 17 12 10BO1 10AI1 GTL outputs LVTTL inputs 1 16 13 10BO2 10AI2 15 9AO LVTTL output 002aac745 (1) The enable on 7BO1/7BO2 include a delay that prevents the transient condition (where 5BI/6BI go from LOW to HIGH, and the LOW to HIGH on 5A/6A lags up to 100 ns) from causing a LOW glitch on the 7BO1/7BO2 outputs. Fig 1. Logic diagram of GTL2107 GTL2107 5 NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 23 December 2009 2 of 19