HEF4044B
Quad R/S latch with 3-state outputs
Rev. 10 18 November 2011 Product data sheet
1. General description
The HEF4044B is a quad R/S latch with 3-state outputs, with a common output enable
input (OE). Each latch has an active LOW set input (1S to 4S), an active LOW reset input
(1R to 4R) and an active HIGH 3-state output (1Q to 4Q).
When OE is HIGH, the latch output (nQ) is determined by the nR and nS inputs as shown
in Table 3. When OE is LOW, the latch outputs are in the high impedance OFF-state. OE
does not affect the state of the latch. The high impedance off-state feature allows common
bussing of the outputs.
It operates over a recommended V power supply range of 3 V to 15 V referenced to V
DD SS
(usually ground). Unused inputs must be connected to V , V , or another input.
DD SS
2. Features and benefits
Fully static operation
5 V, 10 V, and 15 V parametric ratings
Standardized symmetrical output characteristics
Specified from 40 C to +85 C
Complies with JEDEC standard JESD 13-B
3. Applications
Four-bit storage with output enable
4. Ordering information
Table 1. Ordering information
All types operate from 40 C to +85 C.
Type number Package
Name Description Version
HEF4044BP DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
HEF4044BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1HEF4044B
NXP Semiconductors
Quad R/S latch with 3-state outputs
5. Functional diagram
3 1S
1Q 13
4 1R
7 2S
2Q 9
6 2R
nS
3-STATE
OUTPUTS
11 3S
3Q 10
12 3R
nQ
nR
15 4S
4Q 1
14 4R
OE
5 OE
to other latches
001aae621 001aai542
Fig 1. Functional diagram Fig 2. Logic diagram for one latch
6. Pinning information
6.1 Pinning
HEF4044B
4Q 1 16 V
DD
n.c. 2 15 4S
3 14
1S 4R
1R 4 13 1Q
OE 5 12 3R
2R 6 11 3S
2S 7 10 3Q
8 9
V 2Q
SS
001aae622
Fig 3. Pin configuration
HEF4044B All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 10 18 November 2011 2 of 14