HEF4094BP

HEF4094B 8-stage shift-and-store register Rev. 11 29 August 2013 Product data sheet 1. General description The HEF4094B is an 8-stage serial shift register. It has a storage latch associated with each stage for strobing data from the serial input to parallel buffered 3-state outputs QP0 to QP7. The parallel outputs may be connected directly to common bus lines. Data is shifted on positive-going clock transitions. The data in each shift register stage is transferred to the storage register when the strobe (STR) input is HIGH. Data in the storage register appears at the outputs whenever the output enable (OE) signal is HIGH. Two serial outputs (QS1 and QS2) are available for cascading a number of HEF4094B devices. Serial data is available at QS1 on positive-going clock edges to allow high-speed operation in cascaded systems with a fast clock rise time. The same serial data is available at QS2 on the next negative going clock edge. This is used for cascading HEF4094B devices when the clock has a slow rise time. It operates over a recommended V power supply range of 3 V to 15 V referenced to V DD SS (usually ground). Unused inputs must be connected to V , V , or another input. DD SS 2. Features and benefits Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Specified from 40 C to +85 C and 40 C to +125 C Complies with JEDEC standard JESD 13-B 3. Ordering information Table 1. Ordering information All types operate from 40 C to +125 C. Type number Package Name Description Version HEF4094BP DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 HEF4094BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 HEF4094BTS SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 HEF4094BTT TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1HEF4094B NXP Semiconductors 8-stage shift-and-store register 4. Functional diagram 31 CP STR D QS1 9 2 8-STAGE SHIFT QS2 10 QS2 10 CP REGISTER 3 QS1 QP0 4 9 QP1 5 STR 8-BIT STORAGE 1 REGISTER QP2 6 2 D QP3 7 QP4 14 OE 15 3-STATE OUTPUTS QP5 13 QP0 QP1 QP2 QP3 QP4 QP5 QP6 QP7 QP6 12 QP7 11 4 5 6 7 14 13 12 11 001aaf119 OE 15 001aaf111 Fig 1. Functional diagram Fig 2. Logic symbol STAGE 0 STAGES 1 TO 6 STAGE 7 D D Q D Q D Q QS1 CP CP D Q QS2 FF 0 FF 7 CP CP LE LATCH D Q D Q LE LE LATCH 0 LATCH 7 STR OE QP0 QP2 QP4 QP6 001aag799 QP1 QP3 QP5 QP7 Fig 3. Logic diagram HEF4094B All information provided in this document is subject to legal disclaimers. NXP B.V. 2013. All rights reserved. Product data sheet Rev. 11 29 August 2013 2 of 20