HEF4511BP,652

HEF4511B BCD to 7-segment latch/decoder/driver Rev. 7 11 November 2011 Product data sheet 1. General description The HEF4511B is a BCD to 7-segment latch/decoder/driver with four address inputs (D0 to D3), an active HIGH latch enable input (LE), an active LOW ripple blanking input (BL), an active LOW lamp test input (LT), and seven active HIGH NPN bipolar transistor segment outputs (Qa to Qg). When LE is LOW and BL is HIGH, the state of the segment outputs (Qa to Qg) is determined by the data on D0 to D3. When LE goes HIGH, the last data present on D0 to D3 is stored in the latches and the segment outputs remain unchanged. When LT is LOW, all of the segment outputs are HIGH independent of all other input conditions. With LT HIGH, a LOW on BL forces all segment outputs LOW. The inputs LT and BL do not affect the latch circuit. It operates over a recommended V power supply range of 3 V to 15 V referenced to V DD SS (usually ground). Unused inputs must be connected to V , V , or another input. DD SS 2. Features and benefits Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Specified from 40 C to +85 C and 40 C to +125 C Complies with JEDEC standard JESD 13-B 3. Ordering information Table 1. Ordering information All types operate from 40 C to +125 C. Type number Package Name Description Version HEF4511BP DIP16 plastic dual in-line package 16 leads (300 mil) SOT38-4 HEF4511BT SO16 plastic small outline package 16 leads body width 3.9 mm SOT109-1HEF4511B NXP Semiconductors BCD to 7-segment latch/decoder/driver 4. Functional diagram 7 1 2 6 D0 D1 D2 D3 5 LE LATCHES 4 BL DECODER 3 LT DRIVERS Qg Qf Qe Qd Qc Qb Qa 14 15 9 10 11 12 13 001aae675 Fig 1. Functional diagram V DD driver logic I OH + V OH V SS 001aae677 Fig 2. Schematic diagram of output stage HEF4511B All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved. Product data sheet Rev. 7 11 November 2011 2 of 20