MPC8560EC Freescale Semiconductor Rev. 4.2, 1/2008 Technical Data MPC8560 Integrated Processor Hardware Specifications Contents The MPC8560 integrates a PowerPC processor core built 1. Overview . 2 on Power Architecture technology with system logic 2. Electrical Characteristics 8 required for networking, telecommunications, and wireless 3. Power Characteristics 13 infrastructure applications. The MPC8560 is a member of 4. Clock Timing 15 5. RESET Initialization . 17 the PowerQUICC III family of devices that combine 6. DDR SDRAM 18 system-level support for industry-standard interfaces with 7. Ethernet: Three-Speed, MII Management 23 processors that implement the embedded category of the 8. Local Bus . 34 9. CPM . 43 Power Architecture technology. For functional 10. JTAG . 50 characteristics of the processor, refer to the MPC8560 11. I2C 52 PowerQUICC III Integrated Communications Processor 12. PCI/PCI-X . 54 Reference Manual. 13. RapidIO . 58 14. Package and Pin Listings . 70 To locate any published errata or updates for this document, 15. Clocking 80 contact your Freescale sales office. 16. Thermal . 82 17. System Design Information . 92 18. Document Revision History . 99 19. Device Nomenclature . 104 Freescale Semiconductor, Inc., 2008. All rights reserved.Overview 1 Overview The following section provides a high-level overview of the MPC8560 features. Figure 1 shows the major functional units within the MPC8560. 256KB DDR DDR SDRAM Controller L2-Cache/ SDRAM SRAM e500 Core 2 I C Controller e500 32 KB L1 32 KB L1 Coherency GPIO I Cache D Cache Local Bus Controller Module 32b Programmable Core Complex Bus IRQs Interrupt Controller Serial RapidIO-8 CPM RapidIO Controller DMA 16 Gb/s MPHY MCC OCeaN PCI 64b ROM UTOPIAs MCC PCI Controller 133 MHz FCC I-Memory FCC MIIs, DMA Controller FCC RMIIs DPRAM SCC TDMs SCC RISC 10/100/1000 MAC Engine SCC MII, GMII, TBI, I/Os SCC Parallel I/O RTBI, RGMIIs 10/100/1000 MAC SPI Baud Rate Generators I2C Timers CPM Interrupt Controller Figure 1. MPC8560 Block Diagram 1.1 Key Features The following lists an overview of the MPC8560 feature set. High-performance, 32-bit Book Eenhanced core that implements the Power Architecture 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection. Caches can be locked entirely or on a per-line basis. Separate locking for instructions and data Memory management unit (MMU) especially designed for embedded applications Enhanced hardware and software debug support Performance monitor facility (similar to but different from the MPC8560 performance monitor described in Chapter 18, Performance Monitor. High-performance RISC CPM operating at up to 333 MHz CPM software compatibility with previous PowerQUICC families One instruction per clock MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2 2 Freescale Semiconductor Serial Interfaces TC - Layer Time Slot Assigner Time Slot Assigner