Document Number: MC33742 Freescale Semiconductor Rev. 15.0, 12/2014 Technical Data System Basis Chip with 33742 Enhanced High Speed CAN 33742S Transceiver SYSTEM BASIS CHIP The 33742 and the 33742S SMARTMOS devices are SPI-controlled System Basis Chips (SBCs), combining many frequently used functions, along with a CAN 2.0-compliant transceiver, used in many automotive electronic control units (ECUs). The 33742 SBC has a fully protected fixed 5.0 V low dropout internal regulator, with current limiting, overtemperature prewarning, and reset. A second 5.0 V regulator can be EG SUFFIX (PB-FREE) implemented using external pass PNP bipolar junction pass transistor, EP SUFFIX 98ASB42345B (PB-FREE) driven by the SBCs external V2 sense input and V2 output drive pins. 28-PIN SOICW 98ASA00757D The SBC has four main operating modes: Normal, Standby, Stop, and 48-PIN QFN Sleep mode. Additionally, there is an internally switched high side power supply output, four wake-up inputs pins, a programmable window watchdog, interrupt, reset, and a SPI module for communication and ORDERING INFORMATION control. The high speed CAN A and B transceiver is available for intermodule communication. Temperature Device Package Range (T ) A Features MC33742PEG/R2 1.0 Mbps CAN transceiver bus interface with bus diagnostic capability 28 SOICW SPI control at frequencies up to 4.0 MHz MC33742SPEG/R2 - 40 C to 125 C 5.0 V low dropout voltage regulator with current limiting, over- MC33742PEP/R2 48 QFN temperature prewarning, and output monitoring and reset A second 5.0 V regulator capability using an external series pass transistor Normal, Standby, Stop, and Sleep modes of operation with low Sleep and Stop mode current A high side switch output driver for controlling external circuitry V PWR 33742 V2 5.0V VDD VSUP V2CTRL RST V2 MCU V PWR CS CS L0 SCLK SCLK L1 SPI MOSI MOSI L2 MISO MISO L3 Safe WDOG Circuitry INT ECU Local HS Circuitry Twisted TXD CANH CAN Bus CANL RXD Pair GND GND Figure 1. 33742 Simplified Application Diagram Freescale Semiconductor, Inc., 2007-2014. All rights reserved.DEVICE VARIATIONS DEVICE VARIATIONS Table 1. Device Differences During a Reset Condition Part No. Reset Duration Device Differences See Page 33742 15 ms (typical) page 18 The duration the RST pin is asserted low when the Reset mode is entered after the SBC is powered up, a V under-voltage condition is detected, and the DD watchdog register is not properly triggered. 33742S 3.5 ms (typical) page 18 The duration the RST pin is asserted low when the Reset mode is entered after the SBC is powered up, a V under-voltage condition is detected, and the DD watchdog register is not properly triggered. 33742 Analog Integrated Circuit Device Data 2 Freescale Semiconductor