MC33910G5AC/MC3433910G5AC NXP Semiconductors Document Number: MC33910 Rev. 9.0, 7/2016 Technical Data LIN system basis chip with high-side drivers 33910 The 33910G5/BAC is a SMARTMOS Serial Peripheral Interface (SPI) controlled System Basis Chip (SBC), combining many frequently used functions in an MCU based system, plus a Local Interconnect Network (LIN) transceiver. The 33910 SYSTEM BASIS CHIP WITH LIN has a 5.0 V, 50 mA/60 mA low dropout regulator with full protection and reporting ND 2 GENERATION features. The device provides full SPI readable diagnostics and a selectable timing watchdog for detecting errant operation. The LIN Protocol Specification 2.0 and 2.1 compliant LIN transceiver has waveshaping circuitry which can be disabled for higher data rates. Two 50 mA/60 mA high-side switches with optional pulse-width modulated (PWM) are implemented to drive small loads. One high voltage input is available for use in contact monitoring, or as external wake-up input. This input can be used as high voltage Analog Input. The voltage on this pin is divided by a selectable ratio and available via an analog multiplexer. The 33910 has three main operating modes: Normal (all functions available), Sleep (V off, wake-up via LIN, wake-up inputs (L1), cyclic sense and forced DD wake-up), and Stop (V on with limited current capability, wake-up via CS, LIN DD bus, wake-up inputs, cyclic sense, forced wake-up and external reset). AC SUFFIX (Pb-FREE) The 33910 is compatible with LIN Protocol Specification 2.0, 2.1, and 98ASH70029A SAEJ2602-2. 32-PIN LQFP Features Full-duplex SPI interface at frequencies up to 4.0 MHz Applications LIN transceiver capable of up to 100 kbps with wave shaping Window lift Two 50 mA/60 mA high-side switches Mirror switch One high voltage analog/logic Input Door lock Configurable window watchdog Sunroof 5.0 V low drop regulator with fault detection and low voltage reset (LVR) Light control circuitry Switched/protected 5.0 V output (used for Hall sensors) 33910 V BAT VSENSE VS1 HS1 VS2 L1 VDD PWMIN ADOUT0 LIN INTERFACE LIN MCU MOSI MISO SCLK CS RXD HVDD TXD HS2 IRQ RST WDCONF Figure 1. 33910 simplified application diagram 2016 NXP B.V. LGND PGND AGND1 Orderable parts The 33910G5 data sheet is within MC33910G5 product specifications - page 3 to page 49 The 33910BAC data sheet is within MC33911BAC product specifications - page 50 to page 95 (1) Table 1. Orderable part variations Device Temperature Package Changes MC33910G5AC/R2 - 40 C to 125 C Increase ESD GUN IEC61000-4-2 (gun test contact with 150 pF, 330 test conditions) performance to achieve 6.0 kV min on the LIN pin. Immunity against ISO7637 pulse 3b Reduce EMC emission level on LIN MC34910G5AC/R2 - 40 C to 85 C 32 LQFP Improve EMC immunity against RF target new specification including 3x68 pF Comply with J2602 conformance test MC33910BAC/R2 - 40 C to 125 C Initial release MC34910BAC/R2 - 40 C to 85 C Notes 1. To order parts in Tape & Reel, add the R2 suffix to the part number. 33910 2 NXP Semiconductors