MC33GD3000EP NXP

MC33GD3000 Three phase field effect transistor Rev. 9.0 27 October 2020 Product data sheet 1 General description The 33GD3000 is a field effect transistor (FET) predriver designed for three phase motor control and similar applications. It meets the stringent requirements of automotive applications and is fully AEC-Q100 grade 1 qualified. The IC contains three high-side FET predrivers and three low-side FET predrivers. Three external bootstrap capacitors provide gate charge to the high-side FETs. The IC interfaces to a MCU via six direct input control signals, an SPI port for device setup and asynchronous reset, enable and interrupt signals. Both 5.0 and 3.0 V logic level inputs are accepted and 5.0 V logic level outputs are provided. The integrated circuit (IC) uses SMARTMOS technology. 2 Features and benefits Extended operating range from 6.0 V to 60 V covers 12 V and 48 V systems Gate drive capability of 1.0 A to 2.5 A Fully specified from 8.0 V to 40 V, covers 12 and 24 V automotive systems Device protection against reverse charge-injection from C and C of external FETs GD GS Dead time is programmable via the SPI port Simultaneous output capability enabled via safe SPI command AEC-Q100 grade 1 qualified 3 Applications Automotive systems: Cooling fan Water pump Actuator controls Fuel pump Electro-hydraulic and electric power steering Engine and transmission control Motor control Braking pump Belt starter generator Turbo pumpNXP Semiconductors MC33GD3000 Three phase field effect transistor 4 Ordering information Table 1.Ordering information Type number Package Name Description Version MC33GD3000EP HVQFN56 Plastic, thermal enhanced very thin quad flatpack no leads 56 SOT684-17 terminals 0.5 mm pitch 8 mm x 8 mm x 0.9 mm body 5 Block diagram PUMP VPWR VSUP VPUMP MAIN CHARGE TRICKLE HOLD PGND PUMP CHARGE -OFF PUMP CIRCUIT 5.0 V VLS REG. REG. VDD VLS OSCILLATOR VDD UV DETECT 3x PX BOOT RST T-LIM INT HIGH- PX HS G VSUP EN1 SIDE EN2 DRIVER DESAT. 1.4 V PX HS 3 CONTROL COMP. LOGIC PX LS 3 PX HS S CS SI VSUP SCLK SO PHASE LOW- COMP. PX LS G PHASEX SIDE 3 DRIVER OC OUT PX LS S GND(2) OVERCUR. I-SENSE COMP. AMP. VSS OC TH AMP OUT AMP N AMP P VLS CAP aaa-038791 Figure 1.Internal block diagram MC33GD3000 All information provided in this document is subject to legal disclaimers. NXP B.V. 2020. All rights reserved. Product data sheet Rev. 9.0 27 October 2020 2 / 53