MCF5372LCVM240J NXP

Freescale Semiconductor Document Number: MCF5373DS Rev. 4, 11/2008 Data Sheet: Technical Data MCF5373 MAPBGA256 MAPBGA196 17mm x 17mm 15mm x 15mm QFP160 MCF537x ColdFire 28mm x 28mm Microprocessor Data Sheet Features Version 3 ColdFire variable-length RISC processor core System debug support JTAG support for system level board testing On-chip memories 16-Kbyte unified write-back cache 32-Kbyte dual-ported SRAM on CPU internal bus, accessible by core and non-core bus masters (e.g., DMA, FEC, and USB host and OTG) Power management Embedded Voice-over-IP (VoIP) system solution SDR/DDR SDRAM Controller Universal Serial Bus (USB) Host Controller Universal Serial Bus (USB) On-the-Go (OTG) controller Synchronous Serial Interface (SSI) Fast Ethernet Controller (FEC) Cryptography Hardware Accelerators FlexCAN Module Three Universal Asynchronous Receiver Transmitters (UARTs) 2 I C Module Queued Serial Peripheral Interface (QSPI) Pulse Width Modulation (PWM) module Real Time Clock Four 32-bit DMA Timers Software Watchdog Timer Four Periodic Interrupt Timers (PITs) Phase Locked Loop (PLL) Interrupt Controllers (x2) DMA Controller FlexBus (External Interface) Chip Configuration Module (CCM) Reset Controller General Purpose I/O interface Freescale Semiconductor, Inc., 2008. All rights reserved.Table of Contents 1MCF537x Family Comparison .3 5.7.1 SDR SDRAM AC Timing Characteristics . 21 2 Ordering Information .4 5.7.2 DDR SDRAM AC Timing Characteristics . 23 3 Hardware Design Considerations .5 5.8 General Purpose I/O Timing 26 3.1 PLL Power Filtering .5 5.9 Reset and Configuration Override Timing 27 3.2 USB Power Filtering 5 5.10 USB On-The-Go . 28 3.3 Supply Voltage Sequencing and Separation Cautions 5 5.11 SSI Timing Specifications 28 2 3.3.1 Power Up Sequence 5 5.12 I C Input/Output Timing Specifications 29 3.3.2 Power Down Sequence 6 5.13 Fast Ethernet AC Timing Specifications . 31 4 Pin Assignments and Reset States .6 5.13.1 MII Receive Signal Timing 31 4.1 Signal Multiplexing .6 5.13.2 MII Transmit Signal Timing 31 4.2 Pinout196 MAPBGA .12 5.13.3 MII Async Inputs Signal Timing 32 4.3 Pinout160 QFP .13 5.13.4 MII Serial Management Channel Timing . 32 5 Electrical Characteristics 14 5.14 32-Bit Timer Module Timing Specifications . 33 5.1 Maximum Ratings .14 5.15 QSPI Electrical Specifications . 33 5.2 Thermal Characteristics 15 5.16 JTAG and Boundary Scan Timing 34 5.3 ESD Protection .16 5.17 Debug AC Timing Specifications . 36 5.4 DC Electrical Specifications .16 6 Current Consumption 36 5.5 Oscillator and PLL Electrical Characteristics 17 7 Package Information . 39 5.6 External Interface Timing Characteristics .18 7.1 Package Dimensions196 MAPBGA . 40 5.6.1 FlexBus .19 7.2 Package Dimensions160 QFP . 41 5.7 SDRAM Bus .21 8 Revision History 43 MCF537x ColdFire Microprocessor Data Sheet, Rev. 4 2 Freescale Semiconductor