Document Number: MD8IC925N
Freescale Semiconductor
Rev. 0, 5/2013
Technical Data
RF LDMOS Wideband Integrated
Power Amplifiers
MD8IC925NR1
The MD8IC925N wideband integrated circuit is designed with onchip
MD8IC925GNR1
matching that makes it usable from 728 to 960 MHz. This multistage
structure is rated for 24 to 32 volt operation and covers all typical cellular base
station modulation formats.
Driver Application 900 MHz 728960 MHz, 2.5 W AVG., 28 V
SINGLE WCDMA
Typical SingleCarrier WCDMA Performance: V = 28 Volts,
DD
RF LDMOS WIDEBAND
I = 58 mA, I = 222 mA, P = 2.5 Watts Avg., IQ Magnitude
DQ1(A+B) DQ2(A+B) out
INTEGRATED POWER AMPLIFIERS
Clipping, Channel Bandwidth = 3.84 MHz, Input Signal PAR = 7.5 dB
@ 0.01% Probability on CCDF.
G PAE ACPR
ps
Frequency (dB) (%) (dBc)
920 MHz 36.2 17.5 48.9
940 MHz 36.2 17.4 49.5
TO270WB14
960 MHz 36.1 17.3 49.1
PLASTIC
MD8IC925NR1
Capable of Handling 10:1 VSWR, @ 32 Vdc, 940 MHz, 25 Watts CW
Output Power (3 dB Input Overdrive from Rated P )
out
Typical P @ 1 dB Compression Point 26 Watts CW
out
Driver Application 700 MHz
Typical SingleCarrier WCDMA Performance: V = 28 Volts,
DD
I = 58 mA, I = 222 mA, P = 2.5 Watts Avg., IQ Magnitude
DQ1(A+B) DQ2(A+B) out
Clipping, Channel Bandwidth = 3.84 MHz, Input Signal PAR = 7.5 dB
TO270WBG14
@ 0.01% Probability on CCDF.
PLASTIC
MD8IC925GNR1
G PAE ACPR
ps
Frequency (dB) (%) (dBc)
728 MHz 36.4 17.2 48.9
748 MHz 36.4 17.6 49.7
768 MHz 36.4 17.9 50.5
Features
Characterized with Series Equivalent LargeSignal Impedance Parameters
and Common Source SParameters
OnChip Matching (50 Ohm Input, DC Blocked)
Integrated Quiescent Current Temperature Compensation with
(1)
Enable/Disable Function
Integrated ESD Protection
Designed for Digital Predistortion Error Correction Systems
Optimized for Doherty Applications
225C Capable Plastic Package
In Tape and Reel. R1 Suffix = 500 Units, 44 mm Tape Width, 13inch Reel.
1. Refer to AN1977, Quiescent Current Thermal Tracking Circuit in the RF Integrated Circuit Family and to AN1987, Quiescent Current Control
for the RF Integrated Circuit Device Family. Go to V
DS1A
V 1
DS1A
V 2
GS2A
RF
RF /V
inA
out1 DS2A
14
V 3
GS1A
RF /V
out1 DS2A
RF 4
inA
N.C.
5
N.C. 6
V
GS1A Quiescent Current
(1) N.C. 7
Temperature Compensation
V
GS2A
8
N.C.
RF 9
13 RF /V
inB out2 DS2B
V
GS1B
Quiescent Current
V 10
GS1B
(1)
V Temperature Compensation
V 11
GS2B GS2B
V 12
DS1B
(Top View)
RF
inB RF /V
out2 DS2B
Note: Exposed backside of the package is
V
the source terminal for the transistors.
DS1B
Figure 1. Functional Block Diagram Figure 2. Pin Connections
Table 1. Maximum Ratings
Rating Symbol Value Unit
DrainSource Voltage V 0.5, +65 Vdc
DSS
GateSource Voltage V 0.5, +10 Vdc
GS
Operating Voltage V 32, +0 Vdc
DD
Storage Temperature Range T 65 to +150 C
stg
Case Operating Temperature T 150 C
C
(2,3)
Operating Junction Temperature T 225 C
J
Input Power P 20 dBm
in
Table 2. Thermal Characteristics
(3,4)
Characteristic Symbol Value Unit
Thermal Resistance, Junction to Case R C/W
JC
Case Temperature 77C, 2.5 W CW, 940 MHz
Stage 1, 28 Vdc, I = 58 mA, 940 MHz 5.4
DQ1(A+B)
Stage 2, 28 Vdc, I = 222 mA, 940 MHz 1.8
DQ2(A+B)
Table 3. ESD Protection Characteristics
Test Methodology Class
Human Body Model (per JESD22A114) 1A
Machine Model (per EIA/JESD22A115) A
Charge Device Model (per JESD22C101) I
Table 4. Moisture Sensitivity Level
Test Methodology Rating Package Peak Temperature Unit
Per JESD22A113, IPC/JEDEC JSTD020 3 260 C
1. Refer to AN1977, Quiescent Current Thermal Tracking Circuit in the RF Integrated Circuit Family and to AN1987, Quiescent Current Control
for the RF Integrated Circuit Device Family. Go to