Document Number: IMX8MNIEC NXP Semiconductors Rev. 1, 03/2021 Data Sheet: Technical Data MIMX8MN6CVTIZAA MIMX8MN5CVTIZAA MIMX8MN4CVTIZAA MIMX8MN3CVTIZAA MIMX8MN2CVTIZAA MIMX8MN1CVTIZAA MIMX8MN5CVPIZAA MIMX8MN3CVPIZAA MIMX8MN1CVPIZAA i.MX 8M Nano Applications Processor Datasheet for Industrial Package Information Plastic Package Products FCBGA 14 x 14 mm, 0.5 mm pitch FCBGA 11 x 11 mm, 0.5 mm pitch Ordering Information See Table 3 on page 6 1 i.MX 8M Nano introduction The i.MX 8M Nano application processor represents 1. i.MX 8M Nano introduction . 1 1.1. Block diagram 5 NXPs latest graphics and audio experience combining 1.2. Ordering information . 6 state-of-the-art media-specific features with 2. Modules list . 8 2.1. Recommended connections for unused input/output high-performance processing while optimized for lowest 12 power consumption. 3. Electrical characteristics 14 3.1. Chip-level conditions 14 The i.MX 8M Nano family of processors features 3.2. Power supplies requirements and restrictions . 27 3.3. PLL electrical characteristics 33 advanced implementation of a quad Arm Cor- 3.4. On-chip oscillators 34 tex -A53 core, which operates at speeds of up to 3.6. I/O AC parameters . 36 3.7. Output buffer impedance parameters . 37 1.4 GHz. A general purpose Cortex -M7 running up to 3.8. System modules timing 39 3.9. External peripheral interface parameters 40 750 MHz core processor is for real-time and low-power 4. Boot mode configuration 74 processing. 4.1. Boot mode configuration pins . 74 4.2. Boot device interface allocation 74 The i.MX 8M Nano family of processors provides addi- 5. Package information and contact assignments . 76 tional computing resources and peripherals: 5.1. 14 x 14 mm package information 76 Advanced security modules for secure boot, 5.2. 11 x 11 mm package information 92 5.3. DDR pin function list . 107 cipher acceleration and DRM support 6. Revision history 110 A wide range of audio interfaces, including I2S, AC 97, TDM, and S/PDIF Large set of peripherals that are commonly used in consumer/industrial market, including USB and Ethernet NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products. 2019-2021 NXP Semiconductors All rights reserved.i.MX 8M Nano introduction Table 1. Features Subsystem Feature Cortex -A53 MPCore platform Quad symmetric Cortex -A53 processors 32 KB L1 Instruction Cache 32 KB L1 Data Cache TM Media Processing Engine (MPE) with Arm NEON technology supporting the Advanced Single Instruction Multiple Data architecture: Floating Point Unit (FPU) with support of the Arm VFPv4-D16 architecture Support of 64-bit Arm v8-A architecture 512 KB unified L2 cache Cortex -M7 core platform Low power microcontroller available for customer application: low power standby mode IoT features including Weave Manage IR or wireless remote ML inference applications (enhanced for i.MX 8M Nano) Cortex M7 CPU: 256 KB tightly coupled memory (TCM) Connectivity One USB 2.0 OTG controllers with integrated PHY interfaces: Spread spectrum clock support Three Ultra Secure Digital Host Controller (uSDHC) interfaces: MMC 5.1 compliance with HS400 DDR signaling to support up to 400 MB/sec SD/SDIO 3.0 compliance with 200 MHz SDR signaling to support up to 100 MB/sec Support for SDXC (extended capacity) One Gigabit Ethernet controller with support for Energy Efficient Ethernet (EEE), Ethernet AVB, and IEEE 1588 Four Universal Asynchronous Receiver/Transmitter (UART) modules 2 Four I C modules Three SPI modules On-chip memory Boot ROM (256 KB) On-chip RAM (512 KB + 32 KB) GPIO and pin multiplexing General-purpose input/output (GPIO) modules with interrupt capability Input/output multiplexing controller (IOMUXC) to provide centralized pad control Power management Temperature sensor with programmable trip points Flexible power domain partitioning with internal power switches to support efficient power management i.MX 8M Nano Applications Processor Datasheet for Industrial Products, Rev. 1, 03/2021 2 NXP Semiconductors