NXP Semiconductors Document Number: MMPF0100Z Rev. 12.0, 8/2016 Data sheet: Advance Information 14 channel configurable power PF0100Z management integrated circuit Automotive The SMARTMOS PF0100Z AEC Q100 grade 2 automotive power management integrated circuit (PMIC) provides a highly programmable/ configurable POWER MANAGEMENT architecture, with fully integrated power devices and minimal external components. With up to six buck converters, six linear regulators, RTC supply, and coin-cell charger, the PF0100Z can provide power for a complete system, including applications processors, memory, and system peripherals, in a wide range of applications. With on-chip one time programmable (OTP) memory, the PF0100Z is available in pre-programmed standard versions, or non- programmed to support custom programming. The PF0100Z is especially suited to the i.MX 6 family of devices and is supported by full system level reference designs, and pre-programmed versions of the device. ES SUFFIX (WF-TYPE) 98ASA00589D 56 QFN 8X8 Features: Applications: Four to six buck converters, depending on configuration GPS Single/dual phase/ parallel options Auto infotainment DDR termination tracking mode option Heads up display (HUD) Boost regulator to 5.0 V output Rear displays Six general purpose linear regulators Digital instrumentation cluster (DIC) Programmable output voltage, sequence, and timing OTP (one time programmable) memory for device configuration Coin cell charger and RTC supply DDR termination reference voltage Power control logic with processor interface and event detection 2 I C control Individually programmable on, off, and standby modes PF0100Z i.MX 6X VREFDDR DDR MEMORY SW4 DDR Memory INTERFACE 1000 mA SW3A/B 2500 mA SW1A/B Processor Core 2500 mA Voltages SW1C 2000 mA External AMP Microphones SW2 Speakers SATA - FLASH 2000 mA SD-MMC/ SATA NAND - NOR NAND Mem. HDD SWBST Interfaces 600 mA Audio Codec Control Signals Parallel control/GPIOS 2 2 Sensors I C Communication I C Communication VGEN1 Camera 100 mA Camera VGEN2 GPS WAM 250 mA MIPI GPS uPCIe VGEN3 MIPI 100 mA VGEN4 HDMI 350 mA LDVS Display VGEN5 100 mA USB LICELL VGEN6 Ethernet Charger 200 mA CAN Main Supply COINCELL 2.8 4.5 V Front USB Rear Seat Rear USB Cluster/HUD POD Infotaiment POD Figure 1. Simplified application diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. 2016 NXP B.V.Table of Contents 1 Orderable parts 4 2 Internal block diagram . 5 3 Pin connections 6 3.1 Pinout diagram . 6 3.2 Pin definitions . 7 4 General product characteristics 9 4.1 Absolute maximum ratings . 9 4.2 Thermal characteristics . 10 4.2.1 Power dissipation . 10 4.3 Electrical characteristics 11 4.3.1 General Specifications . 11 4.3.2 Current consumption 12 5 General description 14 5.1 Features . 14 5.2 Functional block diagram 15 5.3 Functional description 15 5.3.1 Power generation . 15 5.3.2 Control logic . 15 6 Functional block requirements and behaviors 17 6.1 Start-up . 17 6.1.1 Device start-up configuration 17 6.1.2 One time programmability (OTP) . 20 6.1.3 OTP prototyping 22 6.1.4 Reading OTP fuses . 22 6.1.5 Programming OTP fuses . 22 6.2 16 MHz and 32 kHz clocks 23 6.2.1 Clock adjustment . 23 6.3 Bias and references block description 23 6.3.1 Internal core voltage references . 23 6.3.2 VREFDDR voltage reference 24 6.4 Power generation 27 6.4.1 Modes of operation . 27 6.4.2 State machine flow summary 29 6.4.3 Power tree 31 6.4.4 Buck regulators 33 6.4.5 Boost regulator . 72 6.4.6 LDO regulators description . 75 6.4.7 VSNVS LDO/switch . 90 6.5 Control interface I2C block description . 95 6.5.1 I2C device ID 95 6.5.2 I2C operation 95 6.5.3 Interrupt handling . 96 6.5.4 Interrupt bit summary 96 6.5.5 Specific registers 101 6.5.6 Register Bitmap . 102 PF0100Z 2 NXP Semiconductors