Document Number MPC5748G Freescale Semiconductor Rev. 3, 05/2015 Data Sheet: Technical Data MPC5748G MPC5748G Microcontroller Data Sheet Features Boot Assist Flash (BAF) supports internal flash programming via a serial link (LIN / SCI) 2 x 160 MHz Power Architecture e200Z4 Dual issue, 32-bit CPU Analog Single precision floating point operations Two analog-to-digital converters (ADC), one 10-bit 8 KB instruction cache and 4 KB data cache and one 12-bit Variable length encoding (VLE) for significant code Three analogue comparators density improvements Cross Trigger Unit to enable synchronization of ADC conversions with a timer event from the 1 x 80 MHz Power Architecture e200Z2 Single issue, eMIOS or from the PIT 32-bit CPU Using variable length encoding (VLE) for Communication significant code size footprint reduction Four Deserial Peripheral Interface (DSPI) Six Serial Peripheral interface (SPI) End to end ECC 18 serial communication interface (LIN) modules All bus masters, for example, cores generate single Eight enhanced FlexCAN3 with FD support error correction, double error detection (SECDED) Four inter-IC communication interface (IIC) code for every bus transaction One USB OTG Controller (USB 0) and One USB SECDED covers 64-bit data and 29-bit address SPH Controller (USB 1) with ULPI Interface. Memory interfaces ENET complex (10/100 Ethernet) that supports 6 MB on-chip flash supported with the flash Multi queue with AVB support, 1588, and MII/ controller RMII 3 x flash page buffers (3 port flash controller) 2 x ENET with L2 switch 768 KB on-chip SRAM across three RAM ports Secure Digital Hardware Controller (uSDHC) Dual-channel FlexRay Controller Clock interfaces 8-40 MHz external crystal (FXOSC) Audio 16 MHz IRC (FIRC) 3 x Synchronous Audio Interface (SAI) 128 KHz IRC (SIRC) Fractional clock dividers (FCD) operating in 32 KHz external crystal (SXOSC) conjunction with the SAIs Clock Monitor Unit (CMU) Configurable I/O domains supporting FLEXCAN, Frequency modulated phase-locked loop (FMPLL) LINFlex, Ethernet, USB, MLB, uSDHC and general Real Time Counter (RTC) I/O System Memory Protection Unit (SMPU) with up to 32 Supports wake-up from low power modes via the region descriptors and 16-byte region granularity WKPU controller 16 Semaphores to manage access to shared resource On-chip voltage regulator (VREG) Interrupt controller (INTC) capable of routing Debug functionality interrupts to any CPU e200Z2 core:NDI per IEEE-ISTO 5001-2008 Multiple crossbar switch architecture for concurrent Class3+ access to peripherals, flash, and RAM from multiple e200Z4 core(s): NDI per IEEE-ISTO 5001-2008 bus masters Class 3+ 32-channels eDMA controller with multiple transfer request sources using DMAMUX 20132015 Freescale Semiconductor, Inc. Timer 16 Periodic Interrupt Timers (PITs) Three System Timer Module (STM) Four Software WatchDog Timers (SWT) 96 Configurable Enhanced Modular Input Output Subsystem (eMIOS) channels Device/board boundary Scan testing supported with per Joint Test Action Group (JTAG) of IEEE (IEEE 1149.1) and 1149.7 (cJTAG) Security Hardware Security Module (HSMv2) Password and Device Security (PASS and TDM) supporting advanced censorship and life-cycle management One Fault Collection and Control Unit (FCCU) to collect faults and issue interrupts Functional Safety ISO26262 ASIL compliance Multiple operating modes Includes enhanced low power operation MPC5748G Microcontroller Data Sheet, Rev. 3, 05/2015 2 Freescale Semiconductor, Inc.