MPC8245EC
Freescale Semiconductor
Rev. 10, 08/2007
Technical Data
MPC8245 Integrated Processor
Hardware Specifications
Contents
The MPC8245 combines a PowerPC MPC603e processor
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
core built on Power Architecture technology with a PCI
2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
bridge so that system designers can rapidly design systems
3. General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4. Electrical and Thermal Characteristics . . . . . . . . . . . . 5
using peripherals designed for PCI and the other standard
5. Package Description . . . . . . . . . . . . . . . . . . . . . . . . . 31
interfaces. Also, a high-performance memory controller
6. PLL Configurations . . . . . . . . . . . . . . . . . . . . . . . . . 39
supports various types of ROM and SDRAM. The MPC8245
7. System Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
is the second of a family of products that provide
8. Document Revision History . . . . . . . . . . . . . . . . . . . 56
9. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 62
system-level support for industry-standard interfaces with an
MPC603e processor core.
This hardware specification describes pertinent electrical
and physical characteristics of the MPC8245. For functional
characteristics of the processor, refer to the MPC8245
Integrated Processor Reference Manual (MPC8245UM).
For published errata or updates to this document, visit the
website listed on the back cover of the document.
1Overview
The MPC8245 integrated processor is composed of a
peripheral logic block and a 32-bit superscalar MPC603e
core, as shown in Figure 1.
Freescale Semiconductor, Inc., 20012007. All rights reserved.Overview
MPC8245 Processor Core Block (64-Bit) Two-Instruction Fetch
Additional Features:
Processor
Prog I/O with Watchpoint
Branch
PLL
Processing
JTAG/COP Interface
Instruction Unit
Unit
Power Management
(BPU)
(64-Bit) Two-Instruction Dispatch
System Floating-
Integer Load/Store
Register Point
Unit Unit
Unit Unit
(IU) (LSU)
(SRU) (FPU)
64-Bit
Data Instruction
MMU MMU
16-Kbyte 16-Kbyte
Data Instruction
Cache Cache
Peripheral Logic Bus
Peripheral Logic Block
Data Bus
Data (64-Bit)
Address
Data Path (32- or 64-Bit)
(32-Bit)
Message ECC Controller with 8-Bit Parity
or ECC
Unit
(with I O)
2
Central
Memory
Memory/ROM/
Control
Controller
PortX Control/Address
Unit
DMA
Controller
Performance
Monitor
SDRAM_SYNC_IN
2
2
I C
I C
Controller SDRAM Clocks
DLL
Peripheral Logic
PCI_SYNC_IN
PLL
PIC
5 IRQs/
Interrupt
Configuration
16 Serial
Controller/
Interrupts Registers
Timers
PCI Bus
DUART
Interface Unit
Address PCI
Watchpoint
Fanout
PCI Bus
Translator Arbiter
Facility
Buffers
Clocks
Five
32-Bit
OSC_IN
PCI Interface Request/Grant Pairs
Figure 1. MPC8245 Block Diagram
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
2 Freescale Semiconductor