Document Number:MPC8309EC Freescale Semiconductor Rev 4, 12/2014 Technical Data MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications Contents This document provides an overview of the MPC8309 1. Overview . 2 PowerQUICC II Pro processor features. The MPC8309 is a 2. Electrical Characteristics 7 cost-effective, highly integrated communications processor 3. Power Characteristics 11 that addresses the requirements of several networking 4. Clock Input Timing 12 5. RESET Initialization . 13 applications, including residential gateways, 6. DDR2 SDRAM . 14 modem/routers, industrial control, and test and measurement 7. Local Bus . 19 applications. The MPC8309 extends current PowerQUICC 8. Ethernet and MII Management . 22 9. TDM/SI . 30 offerings, adding higher CPU performance, additional 10. HDLC 31 functionality, and faster interfaces, while addressing the 11. PCI 33 requirements related to time-to-market, price, power 12. USB 36 consumption, and board real estate. This document describes 13. DUART . 38 14. eSDHC . 39 the electrical characteristics of MPC8309. 15. FlexCAN 41 2 To locate published errata or updates for this document, refer 16. I C . 42 17. Timers 44 to the MPC8309 product summary page on our website 18. GPIO . 45 listed on the back cover of this document or contact your 19. IPIC 46 local Freescale sales office. 20. SPI . 46 21. JTAG . 48 22. Package and Pin Listings . 52 23. Clocking 65 24. Thermal . 72 25. System Design Information . 75 26. Ordering Information 78 27. Document Revision History . 80 2011, 2014 Freescale Semiconductor, Inc. All rights reserved. Overview 1 Overview The MPC8309 incorporates the e300c3 (MPC603e-based) core built on Power Architecture technology, which includes 16 Kbytes of each L1 instruction and data caches, dual integer units, and on-chip memory management units (MMUs). The MPC8309 also includes a 32-bit PCI controller, two DMA engines and a 16/32-bit DDR2 memory controller with 8-bit ECC. A new communications complex based on QUICC Engine technology forms the heart of the networking capability of the MPC8309. The QUICC Engine block contains several peripheral controllers and a 32-bit RISC controller. Protocol support is provided by the main workhorses of the devicethe unified communication controllers (UCCs). A block diagram of the MPC8309 is shown in the following figure. 2x DUART e300c3 Core with Power I2C Management Timers 16-KB 16-KB GPIO I-Cache D-Cache ULPI SPI Interrupt DDR2 Enhanced RTC USB 2.0 HS FPU Controller Local Bus Controller Host/Device/OTG IO eSDHC DMA QUICC Engine Block 4 FlexCAN Sequencer Engine 2 16 KB Multi-User RAM Accelerators 48 KB Instruction RAM Baud Rate DMA Generators PCI Controller Serial DMA Single 32-bit RISC CP Engine 1 Time Slot Assigner Serial Interface 2 RMII/MII 2x TDM Ports 1 RMII/MII 2x IEEE 1588 2x HDLC Figure 1. MPC8309 Block Diagram Each of the five UCCs can support a variety of communication protocols such as 10/100 Mbps MII/RMII Ethernet, HDLC and TDM. In summary, the MPC8309 provides users with a highly integrated, fully programmable communications processor. This helps to ensure that a low-cost system solution can be quickly developed and offers flexibility to accommodate new standards and evolving system requirements. MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3 2 Freescale Semiconductor UCC1 UCC2 UCC3 UCC5 UCC7