Document Number: MPC8343EAEC Freescale Semiconductor Rev. 11, 09/2011 Technical Data MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications Contents The MPC8343EA PowerQUICC II Pro is a next generation 1. Overview . 2 PowerQUICC II integrated host processor. The 2. Electrical Characteristics 6 MPC8343EA contains a processor core built on Power 3. Power Characteristics 10 Architecture technology with system logic for networking, 4. Clock Input Timing 11 5. RESET Initialization . 13 storage, and general-purpose embedded applications. For 6. DDR and DDR2 SDRAM . 15 functional characteristics of the processor, refer to the 7. DUART . 21 MPC8349EA PowerQUICC II Pro Integrated Host 8. Ethernet: Three-Speed Ethernet, MII Management . 22 9. USB 30 Processor Family Reference Manual. 10. Local Bus . 31 To locate published errata or updates for this document, refer 11. JTAG . 37 2 12. I C . 41 to the MPC8343EA product summary page on our website, 13. PCI 43 as listed on the back cover of this document, or contact your 14. Timers 45 local Freescale sales office. 15. GPIO . 46 16. IPIC 47 17. SPI . 47 18. Package and Pin Listings . 49 19. Clocking 60 20. Thermal . 68 21. System Design Information . 73 22. Ordering Information 76 23. Document Revision History . 78 20062011 Freescale Semiconductor, Inc. All rights reserved.Overview NOTE The information in this document is accurate for revision 3.x silicon and later (in other words, for orderable part numbers ending in A or B). For information on revision 1.1 silicon and earlier versions, see the MPC8343E PowerQUICC II Pro Integrated Host Processor Hardware Specifications. See Section 22.1, Part Numbers Fully Addressed by This Document, for silicon revision level determination. 1 Overview This section provides a high-level overview of the device features. Figure 1 shows the major functional units within the MPC8343EA. e300 Core DUART 2 Dual I C DDR Timers Interrupt 32KB 32KB Security Local Bus SDRAM GPIO Controller D-Cache I-Cache Controller High-Speed 10/100/1000 10/100/1000 SEQ USB 2.0 PCI DMA Ethernet Ethernet Dual Role Figure 1. MPC8343EA Block Diagram Major features of the device are as follows: Embedded PowerPC e300 processor core operates at up to 400 MHz High-performance, superscalar processor core Floating-point, integer, load/store, system register, and branch processing units 32-Kbyte instruction cache, 32-Kbyte data cache Lockable portion of L1 cache Dynamic power management Software-compatible with the other Freescale processor families that implement Power Architecture technology Double data rate, DDR1/DDR2 SDRAM memory controller Programmable timing supporting DDR1 and DDR2 SDRAM 32- bit data interface, up to 266 MHz data rate MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11 2 Freescale Semiconductor