Document Number: MPC8358EEC Freescale Semiconductor Rev. 3, 01/2011 Technical Data MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications Contents This document provides an overview of the MPC8358E 1. Overview 2 PowerQUICC II Pro processor revision 2.1 PBGA features, 2. Electrical Characteristics 7 including a block diagram showing the major functional 3. Power Characteristics . 12 components. This device is a cost-effective, highly 4. Clock Input Timing . 13 5. RESET Initialization 15 integrated communications processor that addresses the 6. DDR and DDR2 SDRAM 18 needs of the networking, wireless infrastructure, and 7. DUART 25 telecommunications markets. Target applications include 8. UCC Ethernet Controller: Three-Speed Ethernet, MII Management . 25 next generation DSLAMs, network interface cards for 3G 9. Local Bus . 39 base stations (Node Bs), routers, media gateways, and high 10. JTAG 45 end IADs. The device extends current PowerQUICC II Pro 2 11. I C 49 12. PCI 51 offerings, adding higher CPU performance, additional 13. Timers . 53 functionality, faster interfaces, and robust interworking 14. GPIO 54 between protocols while addressing the requirements related 15. IPIC . 55 to time-to-market, price, power, and package size. This 16. SPI 55 17. TDM/SI 57 device can be used for the control plane and also has data 18. UTOPIA/POS . 59 plane functionality. 19. HDLC, BISYNC, Transparent, and Synchronous UART . 61 For functional characteristics of the processor, refer to the 20. USB . 64 MPC8360E PowerQUICC II Pro Integrated 21. Package and Pin Listings . 65 Communications Processor Family Reference Manual, 22. Clocking . 73 23. Thermal 84 Rev. 3. 24. System Design Information . 89 To locate any updates for this document, refer to the 25. Ordering Information 92 26. Document Revision History 94 MPC8360E product summary page on our website listed on the back cover of this document or contact your Freescale sales office. 2011 Freescale Semiconductor, Inc. All rights reserved.Overview 1Overview This section describes a high-level overview including features and general operation of the MPC8358E PowerQUICC II Pro processor. A major component of this device is the e300 core, which includes 32 Kbytes of instruction and data cache and is fully compatible with the Power Architecture 603e instruction set. The new QUICC Engine module provides termination, interworking, and switching between a wide range of protocols including ATM, Ethernet, HDLC, and POS. The QUICC Engine modules enhanced interworking eases the transition and reduces investment costs from ATM to IP based systems. The MPC8358E has a single DDR SDRAM memory controller. The MPC8358E also offers a 32-bit PCI controller, a flexible local bus, and a dedicated security engine. Figure 1 shows the MPC8358E block diagram. System Interface Unit e300 Core (SIU) Security Engine 32KB 32KB Memory Controllers I-Cache D-Cache GPCM/UPM/SDRAM Classic G2 MMUs DDRC 32/64 DDR Interface Unit Power PCI FPU Management PCI Bridge Local JTAG/COP Timers Local Bus Bus Arbitration QUICC Engine Module DUART Multi-User Accelerators RAM Baud Rate Serial DMA Generators & Dual I2C 2 Virtual Dual 32-Bit RISC CP DMAs 4 Channel DMA Parallel I/O Interrupt Controller Protection & Configuration System Reset Time Slot Assigner Clock Synthesizer Serial Interface 6 MII/ 2 GMII/ 1 UTOPIA/POS 4 TDM Ports RMII RGMII/TBI/RTBI (31/124 MPHY) Figure 1. MPC8358E Block Diagram Major features of the MPC8358E are as follows: e300 PowerPC processor core (enhanced version of the MPC603e core) Operates at up to 400 MHz (for the MPC8358E) High-performance, superscalar processor core Floating-point, integer, load/store, system register, and branch processing units MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3 2 Freescale Semiconductor UCC1 UCC2 UCC3 UCC4 UCC5 UCC8 USB SPI1 SPI2