Document Number: MPC8377EEC Freescale Semiconductor Rev. 10, 07/2014 Technical Data MPC8377E PowerQUICC II Pro Processor Hardware Specifications Contents This document provides an overview of the MPC8377E 1. Overview 1 PowerQUICC II Pro processor features, including a block 2. Electrical Characteristics 7 diagram showing the major functional components. This 3. Power Characteristics 11 chip is a cost-effective, low-power, highly integrated host 4. Clock Input Timing . 13 5. RESET Initialization 15 processor that addresses the requirements of several 6. DDR1 and DDR2 SDRAM . 16 printing and imaging, consumer, and industrial 7. DUART 22 applications, including main CPUs and I/O processors in 8. Ethernet: Enhanced Three-Speed Ethernet (eTSEC) 23 9. USB . 32 printing systems, networking switches and line cards, 10. Local Bus . 34 wireless LANs (WLANs), network access servers (NAS), 11. Enhanced Secure Digital Host Controller (eSDHC) 43 VPN routers, intelligent NIC, and industrial controllers. 12. JTAG 51 2 This chip extends the PowerQUICC family, adding higher 13. I C 55 14. PCI 57 CPU performance, additional functionality, and faster 15. PCI Express . 59 interfaces while addressing the requirements related to 16. Serial ATA (SATA) 68 time-to-market, price, power consumption, and package 17. Timers 73 size. 18. GPIO 74 19. IPIC . 74 20. SPI 75 21. High-Speed Serial Interfaces (HSSI) 77 1 Overview 22. Package and Pin Listings . 87 23. Clocking . 106 This chip incorporates the e300c4s core, which includes 24. Thermal . 113 32 KB of L1 instruction and data caches and on-chip 25. System Design Information 119 memory management units (MMUs). The device offers 26. Ordering Information . 121 27. Document Revision History 123 two enhanced three-speed 10, 100, 1000 Mbps Ethernet interfaces, a DDR1/DDR2 SDRAM memory controller, a flexible, a 32-bit local bus controller, a 32-bit PCI controller, an optional dedicated security engine, a USB 2.0 dual-role controller, a programmable interrupt 2008-2012, 2014 Freescale Semiconductor, Inc. All rights reserved. 2 controller, dual I C controllers, a 4-channel DMA controller, an enhanced secured digital host controller, and a general-purpose I/O port. This figure shows the block diagram of the chip. MPC8377E DUART 2 Dual I C e300 Core Timers GPIO 32 KB 32 KB DDR1/DDR2 SPI Enhanced D-Cache I-Cache SDRAM Interrupt Security Local Bus Controller Controller USB 2.0 PCI SD/MMC SATA eTSEC eTSEC Hi-Speed Express Controller PHY PHY x1 x2 RGMII, RMII, RGMII, RMII, DMA PCI Host Device RTBI, MII RTBI, MII Figure 1. MPC8377E Block Diagram and Features The following features are supported in the chip: e300c4s core built on Power Architecture technology with 32 KB instruction cache and 32 KB data cache, a floating point unit, and two integer units DDR1/DDR2 memory controller supporting a 32/64-bit interface Peripheral interfaces, such as a 32-bit PCI interface with up to 66-MT/s operation 32-bit local bus interface running up to 133-MT/s USB 2.0 (full/high speed) support Power management controller for low-power consumption High degree of software compatibility with previous-generation PowerQUICC processor-based designs for backward compatibility and easier software migration Optional security engine provides acceleration for control and data plane security protocols The optional security engine (SEC 3.0) is noted with the extension E at the end. It allows CPU-intensive cryptographic operations to be offloaded from the main CPU core. The security-processing accelerator provides hardware acceleration for the DES, 3DES, AES, SHA-1, and MD-5 algorithms. MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10 2 Freescale Semiconductor