MPC853TVR100A

Freescale Semiconductor, Inc. Advance Information MPC852TTS/D Rev. 1.3, 4/2003 MPC852T PowerQUICC Technical Summary This document provides an overview of the MPC852T PowerQUICC device, describing major functions and features. The MPC852T PowerQUICC device contains a PowerPC processor core. Topic Page Section 1.1, Features 2 Section 1.2, Embedded MPC8xx Core 5 Section 1.3, System Interface Unit (SIU) 6 Section 1.4, PCMCIA Controller 6 Section 1.5, Power Management 7 Section 1.6, Communications Processor Module (CPM) 7 Section 1.7, Document Revision History 7 The MPC852T PowerQUICC is a 0.18 micron version of the MPC860 PowerQUICC Family and can operate up to 100 MHz on the MPC8xx Core with a 66 MHz external bus. The MPC852T has a 1.8 V core and has a 3.3 V I/O operation with 5 V TTL compatibility. The MPC852T Integrated Communications Controller is a versatile one-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications. It particularly excels in both communications and networking systems. The MPC852T is a PowerPC architecture-based derivative of Motorolas MPC860 Quad Integrated Communications Controller (PowerQUICC). The CPU on the MPC852T is the MPC8xx core, a 32-bit microprocessor which implements the PowerPC architecture, incorporating memory management units (MMUs) and instruction and data caches. Table 1 shows the functionality supported by the MPC852T device: Table 1. MPC852T Cache Ethernet Part SCC ATM Support Instruction 10Base Data Cache 10/100 Cache T MPC852T 4 Kbyte 4 Kbyte Up to 2 1 2 No Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Features Features 1.1 Features The following list summarizes the key MPC852T features: Embedded MPC8xx core up to 100 MHz Maximum frequency operation of the external bus is 66 MHz The 100MHz/80MHz core frequencies support 2:1 mode only The 50MHz/66MHz core frequencies support both 1:1 and 2:1 modes Single-issue, 32-bit core (compatible with the PowerPC architecture denition) with 32, 32-bit general-purpose registers (GPRs) The core performs branch prediction with conditional prefetch, without conditional execution 4-Kbyte data cache and 4-Kbyte instruction cache 4-Kbyte instruction cache is two-way, set-associative with 128 sets 4-Kbyte data cache is two-way, set-associative with 128 sets Cache coherency for both instruction and data caches is maintained on 128-bit (4-word) cache blocks Caches are physically addressed, implement a least recently used (LRU) replacement algorithm, and are lockable on a cache block basis MMUs with 32-entry TLB, fully associative instruction and data TLBs MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes 16 virtual address spaces and 16 protection groups Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits) 32 address lines Memory controller (eight banks) Contains complete dynamic RAM (DRAM) controller Each bank can be a chip select or RAS to support a DRAM bank Up to 30 wait states programmable per memory bank Glueless interface to DRAM, SIMMS, SRAM, EPROMs, ash EPROMs, and other memory devices DRAM controller programmable to support most size and speed memory interfaces Four CAS lines, four WE lines, one OE line Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory) Variable block sizes (32 Kbyte256 Mbyte) Selectable write protection On-chip bus arbitration logic Fast Ethernet controller (FEC) General-purpose timers Two 16-bit timers or one 32-bit timer Gate mode can enable/disable counting Interrupt can be masked on reference match and event capture System integration unit (SIU) Bus monitor Software watchdog 2 MPC852T PowerQUICC Technical Summary For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc...