MPC853TEC
Freescale Semiconductor
Rev. 1, 12/2004
Advance Information
MPC853T Hardware Specification
Contents
This hardware specification contains detailed information on the
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
power considerations, DC/AC electrical characteristics, and AC
2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
timing specifications of the MPC853T. The MPC853T contains a
3. Maximum Tolerated Ratings . . . . . . . . . . . . . . . . . . . 6
PowerPC processor core.
4. Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . 7
5. Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
This hardware specification describes pertinent electrical and
6. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
physical characteristics of the MPC853T. For the functional
7. Thermal Calculation and Measurement . . . . . . . . . . . 9
characteristics of the processor, refer to the MPC866
8. Power Supply and Power Sequencing . . . . . . . . . . . 11
PowerQUICC Family Users Manual (MPC866UM). 9. Mandatory Reset Configurations . . . . . . . . . . . . . . . 12
10. Layout Practices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
11. Bus Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 13
12. IEEE 1149.1 Electrical Specifications . . . . . . . . . . . 42
1Overview
13. CPM Electrical Characteristics . . . . . . . . . . . . . . . . . 44
14. FEC Electrical Characteristics . . . . . . . . . . . . . . . . . 63
The MPC853T PowerQUICC is a 0.18-micron derivative of the
15. Mechanical Data and Ordering Information . . . . . . . 67
MPC860 PowerQUICC family. It can operate at up to 100 MHz on
16. References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
the MPC8xx core with a 66-MHz external bus. The MPC853T has
17. Document Revision History . . . . . . . . . . . . . . . . . . . 84
a 1.8-V core and 3.3-V I/O operation with 5-V TTL compatibility.
The MPC853T integrated communications controller is a versatile
one-chip integrated microprocessor and peripheral combination
that can be used in a variety of controller applications. It
particularly excels in Ethernet control applications, including CPE
equipment, Ethernet routers and hubs, VoIP clients, and Wi-Fi
access points.
The MPC853T is a PowerPC architecture-based derivative of
Freescale's MPC860 quad integrated communications controller
(PowerQUICC). The CPU on the MPC853T has a MPC8xx core,
a 32-bit microprocessor that implements the PowerPC architecture
This document contains information on a new product. Specifications and information herein
are subject to change without notice.
Freescale Semiconductor, Inc., 2004. All rights reserved.Features
and incorporates memory management units (MMUs), instruction and data caches. The MPC853T is a subset of this
family of devices and is the main focus of this document.
2Features
The MPC853T is comprised of three modules that each use the 32-bit internal bus: a MPC8xx core, a system
integration unit (SIU), and a communications processor module (CPM). The MPC853T block diagram is shown in
Figure 1.
The following list summarizes the key MPC853T features:
Embedded MPC8xx core up to 100 MHz
Maximum frequency operation of the external bus is 66 MHz
The 50-/66-MHz core frequencies support both the 1:1 and 2:1 modes.
The 80-/100-MHz core frequencies support 2:1 mode only.
Single-issue, 32-bit core (compatible with the PowerPC architecture definition) with thirty-two 32-bit
general-purpose registers (GPRs)
The core performs branch prediction with conditional prefetch and without conditional execution.
4-Kbyte data cache and 4-Kbyte instruction cache
Instruction cache is two-way, set-associative with 128 sets
Data cache is two-way, set-associative with 128 sets
Cache coherency for both instruction and data caches is maintained on 128-bit (4-word) cache
blocks.
Caches are physically addressed, implement a least recently used (LRU) replacement algorithm, and
are lockable on a cache block basis.
MMUs with 32-entry translation look-aside buffer (TLB), fully associative instruction, and data TLBs
MMUs support multiple page sizes of 4 Kbytes, 16 Kbytes, 512 Kbytes, and 8 Mbytes; 16 virtual
address spaces and 16 protection groups
Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)
32 address lines
Memory controller (eight banks)
Contains complete dynamic RAM (DRAM) controller
Each bank can be a chip select or RAS to support a DRAM bank.
Up to 30 wait states programmable per memory bank
Glueless interface to DRAM, SIMMS, SRAM, EPROMs, Flash EPROMs, and other memory devices
DRAM controller programmable to support most size and speed memory interfaces
Four CAS lines, four WE lines, and one OE line
Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)
Variable block sizes (32 Kbytes256 Mbytes)
Selectable write protection
On-chip bus arbitration logic
Fast Ethernet Controller (FEC)
MPC853T Hardware Specification, Rev. 1
2 Freescale Semiconductor