N74F20D,602 NXP

INTEGRATED CIRCUITS 74F20 Dual 4-input NAND gate Product specification 1989 Mar 03 IC15 Data Handbook Philips Semiconductors Product specification Dual 4-input NAND gate 74F20 PIN CONFIGURATION TYPE TYPICAL TYPICAL PROPAGATION SUPPLY CURRENT D0a 1 14 DELAY (TOTAL) V CC D0b 2 13 D1d 74F20 3.5ns 2.2mA NC 3 12 D1c D0c 4 11 NC ORDERING INFORMATION D0d 5 10 D1b COMMERCIAL RANGE DESCRIPTION V = 5V 10%, PKG DWG Q0 6 9 D1a CC T = 0C to +70C amb GND 7 8 Q1 14-pin plastic DIP N74F20N SOT27-1 SF00065 14-pin plastic SO N74F20D SOT108-1 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW Dna, Dnb, Dnc, Dnd Data inputs 1.0/1.0 20A/0.6mA Q0, Q1 Data outputs 50/33 1.0mA/20mA NOTE: One (1.0) FAST unit load is defined as: 20A in the High state and 0.6mA in the Low state. LOGIC DIAGRAM FUNCTION TABLE INPUTS OUTPUT 1 D0a Dna Dnb Dnc Dnd Qn 2 D0b 6 L X X X H Q0 4 D0c X L X X H 5 D0d X X L X H X X X L H 9 D1a H H H H L 10 D1b 8 NOTES: Q1 12 H = High voltage level D1c L = Low voltage level 13 V = Pin 14 CC D1d X = Dont care GND = Pin 7 SF00066 LOGIC SYMBOL IEC/IEEE SYMBOL 12 4 5 9 10 12 13 1 & 2 6 D0a D0b D0c D0d D1a D1b D1c D1d 4 5 Q0 Q1 V = Pin 14 CC 9 GND = Pin 7 68 SF00067 10 8 12 13 SF00068 2 March 3, 1989 8530332 95935