INTEGRATED CIRCUITS
74F573
Octal transparent latch (3-State)
74F574
Octal transparent latch (3-State)
Product specification 1989 Oct 16
IC15 Data Handbook
Philips Semiconductors Product specification
Latch/flip-flop 74F573/74F574
74F573 Octal Transparent Latch (3-State)
74F574 Octal D Flip-Flop (3-State)
The 74F574 is functionally identical to the 74F374 but has a
FEATURES
broadside pinout configuration to facilitate PC board layout and
74F573 is broadside pinout version of 74F373
allow easy interface with microprocesors.
74F574 is broadside pinout version of 74F374
It is an 8-bit, edge triggered register coupled to eight 3-State output
buffers. The two sections of the device are controlled independently
Inputs and Outputs on opposite side of package allow easy
by the clock (CP) and Output Enable (OE) control gates.
interface to Microprocessors
The register is fully edge-triggered. The state of each D input, one
Useful as an Input or Output port for Microprocessors
setup time before the Low-to-High clock transition is transferred to
3-State Outputs for Bus interfacing
the corresponding flip-flops Q output.
Common Output Enable The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. The
74F563 and 74F564 are inverting version of 74F573 and 74F574
active Low Output Enable (OE) controls all eight 3-State buffers
respectively
independently of the latch operation. When OE is Low, the latched
or transparent data appears at the outputs. When OE is High, the
3-State Outputs glitch free during power-up and power-down
outputs are in high impedance off state, which means they will
These are High-Speed replacements for N8TS805 and N8TS806
neither drive nor load the bus.
DESCRIPTION
TYPICAL SUPPLY
TYPICAL
The 74F573 is an octal transparent latch coupled to eight 3-State
TYPE CURRENT
PROPAGATION DELAY
output buffers. The two sections of the device are controlled (TOTAL)
independently by Enable (E) and Output Enable (OE) control gates.
74F573 5.0ns 35mA
The 74F573 is functionally identical to the 74F373 but has a
broadside pinout configuration to facilitate PC board layout and
TYPICAL SUPPLY
allow easy interface with microprocessors.
TYPE TYPICAL f CURRENT
MAX
The data on the D inputs is transferred to the latch outputs when the (TOTAL)
Enable (E) input is High. The latch remains transparent to the data
74F574 180MHz 50mA
input while E is High and stores the data that is present one setup
time before the High-to-Low enable transition.
ORDERING INFORMATION
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. The COMMERCIAL RANGE
DESCRIPTION V = 5V 10%, PKG DWG #
active Low Output Enable (OE) controls all eight 3-State buffers CC
T = 0C to +70C
amb
independent to the latch operation. When OE is Low, the latched or
transparent data appears at the outputs. When OE is High, the
20-Pin Plastic DIP N74F573N, N74F574N SOT146-1
outputs are in high impedance off state, which means they will
20-Pin Plastic SOL N74F573D, N74F574D SOT163-1
neither drive nor load the bus.
20-Pin Plastic SSOP N74F573DB SOT339-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
74F (U.L.) LOAD VALUE
PINS DESCRIPTION
HIGH/LOW HIGH/LOW
D0 - D7 Data inputs 1.0/1.0 20A/0.6mA
E (74F573) Latch Enable input (active falling edge) 1.0/1.0 20A/0.6mA
OE Output Enable input (active Low) 1.0/1.0 20A/0.6mA
CP (74F574) Clock Pulse input (active rising edge) 1.0/1.0 20A/0.6mA
Q0 - Q7 3-State outputs 150/40 3.0mA/24mA
NOTE: One (1.0) FAST Unit Load is defined as: 20A in the High state and 0.6mA in the Low state.
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1989 Oct 16 853-0083 97897