UM10601 LPC81x User manual Rev. 1.6 2 April 2014 User manual Document information Info Content Keywords ARM Cortex M0+, LPC800, LPC800 UM, LPC81x, LPC81x UM, USART, I2C, LPC811M001JDH16, LPC812M101JDH16, LPC812M101JD20, LPC812M101JDH20, LPC810M021FN8, LPC812M101JTB16 Abstract LPC81x user manualUM10601 NXP Semiconductors LPC81x User manual Revision history Rev Date Description 1.6 20140402 LPC81x user manual PDF output size corrected. 1.5 20140306 LPC81x user manual Modifications: Table 147 SCT configuration example corrected. Figure 43 Boot ROM structure corrected. 1.4 20140207 LPC81x user manual Modifications: Editorial updates in the SPI chapter. Bit FLEN renamed to LEN in the TXDATCTL and TXCTL registers. Bit description of the FRAME DELAY bit in the SPI DELAY register updated. See Table 205. Chapter 29 LPC81x Code examples added. SCT behavior in undefined state described in Section 10.7.5. Clarify write access to the following registers in the SCT: COUNT, STATE, MATCH, FRACMAT, and OUTPUT. Writes are only allowed when the counter is halted. Clarify repeated access to SCT CTRL register. Reset value of the SYSAHBCLKCTRL register corrected. See Table 30. Part LPC812M101JTB16 added. Code examples corrected in Chapter 23 LPC81x Power profile API ROM driver, Chapter 25 LPC81x USART API ROM driver routines, and Chapter 24 LPC81x I2C-bus ROM API to comply with LPCOpen code. Remark about 5 V tolerance added for digital pins with configurable open-drain mode. See Section 6.4.4. Description of the EVn STATE register clarified. See Table 142 SCT event state mask registers 0 to 5 (EV 0:5 STATE, addresses 0x5000 4300 (EV0 STATE) to 0x5000 4328 (EV5 STATE)) bit description. Description of SLEEPFLAG bit corrected in the PCON register. Reading a 1 indicates that the part was in sleep, deep-sleep, or power-down mode before wake-up. See Table 55 Register overview: PMU (base address 0x4002 0000). Added recommendation to use a software delay after power-up of the system oscillator. See Section 4.6.32 Power configuration register. Section 4.7.1 Reset, Section 4.7.2 Start-up behavior, Section 4.7.3 Brown-out detection added for clarity. Description of Go command clarified. See Section 22.5.1.8 Go <address> <mode>. Description of the ARM STIR register removed. This register is not implemented in the ARMv6-M architecture. Name SCT changed to SCTimer/PWM for clarity where appropriate throughout the document. Behavior of data stalls for different settings of the SPI TXDATCTL register bit EOT clarified. Section 17.6.7 SPI Transmitter Data and Control register. Add clock frequency parameter to IAP commands Copy RAM to flash, Erase page, and Erase sector. Table 258, Table 259, Table 266. This parameter has been removed in error in v. 1.3. Description of MRT one-shot bus stall mode added. See Section 11.5.3 One-shot bus stall mode and Table 151 Control register (CTRL 0:3 , address 0x4000 4008 (CTRL0) to 0x4000 4038 (CTRL3)) bit description. UM10601 All information provided in this document is subject to legal disclaimers. NXP B.V. 2014. All rights reserved. User manual Rev. 1.6 2 April 2014 2 of 370