PCF8593
Low power clock and calendar
Rev. 04 6 October 2010 Product data sheet
1. General description
1
The PCF8593 is a CMOS clock and calendar circuit, optimized for low power
consumption. Addresses and data are transferred serially via the two-line bidirectional
2
I C-bus. The built-in word address register is incremented automatically after each written
or read data byte. The built-in 32.768 kHz oscillator circuit and the first 8 bytes of the RAM
are used for the clock, calendar, and counter functions. The next 8 bytes can be
programmed as alarm registers or used as free RAM space.
2. Features and benefits
2
I C-bus interface operating supply voltage: 2.5 V to 6.0 V
Clock operating supply voltage 1.0 V to 6.0 V at 0 Cto+70 C
8 bytes scratchpad RAM (when alarm not used)
Data retention voltage: 1.0 V to 6.0 V
2
External RESET input resets I C interface only
Operating current (at f = 0 Hz, 32 kHz time base, V = 2.0 V): typical 1 A
SCL DD
Clock function with four year calendar
Universal timer with alarm and overflow indication
24 hour or 12 hour format
32.768 kHz or 50 Hz time base
2
Serial input and output bus (I C-bus)
Automatic word address incrementing
Programmable alarm, timer, and interrupt function
Space-saving SO8 package available
Slave addresses: A3h for reading, A2h for writing
3. Ordering information
Table 1. Ordering information
Type number Package
Name Description Version
PCF8593P DIP8 plastic dual in-line package; 8 leads (300 mil) SOT97-1
PCF8593T SO8 plastic small outline package; 8 leads; SOT96-1
body width 3.9 mm
1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 14.PCF8593
NXP Semiconductors
Low power clock and calendar
4. Marking
Table 2. Marking codes
Type number Marking code
PCF8593P PCF8593P
PCF8593T 8583T
5. Block diagram
V
DD
OSCI
DIVIDER
OSCILLATOR
OSCO
00h control/status
INT 01h hundredth second
02h seconds
03h minutes
CONTROL
RESET
RESET
LOGIC
04h
hours
year/date
05h
06h
PCF8593 weekdays/months
timer
07h
SCL 08h alarm control
2
I C-BUS ADDRESS
to
INTERFACE REGISTER
alarm or RAM
SDA
0Fh
013aaa379
V
SS
Fig 1. Block diagram of PCF8593
PCF8593 All information provided in this document is subject to legal disclaimers. NXP B.V. 2010. All rights reserved.
Product data sheet Rev. 04 6 October 2010 2 of 35