PN5180A0HN/C1E NXP

PN5180A0xx/C1/C2 High-performance multi-protocol full NFC frontend, supporting all NFC Forum modes Rev. 3.6 7 May 2018 Product data sheet 240936 COMPANY PUBLIC 1 Introduction This document describes the functionality and electrical specification of the high-power NFC IC PN5180A0HN/C1, PN5180A0ET/C1,PN5180A0HN/C2, PN5180A0ET/C2. Additional documents supporting a design-in of the PN5180 are available from NXP, this information is not part of this document.NXP Semiconductors PN5180A0xx/C1/C2 High-performance multi-protocol full NFC frontend, supporting all NFC Forum modes 2 General description PN5180, the best full NFC frontend on the market. As a highly integrated high performance full NFC Forum-compliant frontend IC for contactless communication at 13.56 MHz, this frontend IC utilizes an outstanding modulation and demodulation concept completely integrated for different kinds of contactless communication methods and protocols. The PN5180 ensures maximum interoperability for next generation of NFC enabled mobile phones. The PN5180 is optimized for point of sales terminal applications and implements a high-power NFC frontend functionality which allows to achieve EMV compliance on RF level without additional external active components. The PN5180 frontend IC supports the following RF operating modes: Reader/Writer mode supporting ISO/IEC 14443 type A up to 848 kBit/s Reader/Writer communication mode for MIFARE Classic contactless IC Reader/Writer mode supporting ISO/IEC 14443 type B up to 848 kBit/s Reader/Writer mode supporting JIS X 6319-4 (comparable with FeliCa scheme) Supports reading of all NFC tag types (type 1, type 2, type 3, type 4A and type 4B) Reader/Writer mode supporting ISO/IEC 15693 Reader/Writer mode supporting ISO/IEC 18000-3 Mode 3 ISO/IEC 18092 (NFC-IP1) ISO/IEC 21481 (NFC-IP-2) ISO/IEC 14443 type A Card emulation up to 848 kBit/s One host interface based on SPI is implemented: SPI interface with data rates up to 7 Mbit/s with MOSI, MISO, NSS and SCK signals Interrupt request line to inform host controller on events EEPROM configurable pull-up resistor on SPI MISO line Busy line to indicate to host availability of data for reading The PN5180 supports highly innovative and unique features which do not require any host controller interaction. These unique features include Dynamic Power Control (DPC), Adaptive Waveform Control (AWC), Adaptive Receiver Control (ARC), and fully automatic EMD error handling. The independency of real-time host controller interactions makes this product the best choice for systems which operate a preemptive multi-tasking OS like Linux or Android. As new power-saving feature the PN5180 allows using a general-purpose output to control an external LDO or DC/DC during Low-Power Card Detection. One general- purpose output is used to wake-up an LDO or DC/DC from power-saving mode before the RF field for an LPCD polling cycle is switched on. The PN5180 supports an external silicon system-power-on switch by using the energy of the RF field generated by an NFC phone to switch on the system, like it is generated during the NFC polling loop. This unique and new Zero-Power-Wake-up feature allows designing systems with a power consumption close to zero during standby. PN5180 All information provided in this document is subject to legal disclaimers. NXP B.V. 2018. All rights reserved. Product data sheet Rev. 3.6 7 May 2018 COMPANY PUBLIC 240936 2 / 160