PTN3361C Enhanced performance HDMI/DVI level shifter with active DDC buffer, supporting 1.65 Gbit/s operation Rev. 1.1 28 July 2015 Product data sheet 1. General description PTN3361C is a high-speed level shifter device which converts four lanes of low-swing AC-coupled differential input signals to DVI v1.0 and HDMI v1.4b compliant open-drain current-steering differential output signals, up to 1.65 Gbit/s per lane to support 1080p applications. Each of these lanes provides a level-shifting differential buffer to translate from low-swing AC-coupled differential signaling on the source side, to TMDS-type DC-coupled differential current-mode signaling terminated into 50 to 3.3 V on the sink side. Additionally, PTN3361C provides a single-ended active buffer for voltage translation of the HPD signal from 5 V on the sink side to 3.3 V on the source side and provides a channel with active buffering and level shifting of the DDC channel (consisting of a clock and a data line) between 3.3 V source-side and 5 V sink-side. The DDC channel is 2 implemented using active I C-bus buffer technology providing capacitive isolation, redriving and level shifting as well as disablement (isolation between source and sink) of the clock and data lines. The low-swing AC-coupled differential input signals to PTN3361C typically come from a display source with multi-mode I/O, which supports multiple display standards, for example, DisplayPort, HDMI and DVI. While the input differential signals are configured to carry DVI or HDMI coded data, they do not comply with the electrical requirements of the DVI v1.0 or HDMI v1.4b specification. By using PTN3361C, chip set vendors are able to implement such reconfigurable I/Os on multi-mode display source devices, allowing the support of multiple display standards while keeping the number of chip set I/O pins low. See Figure 1. PTN3361C features low-swing self-biasing differential inputs which are compliant to the electrical specifications of DisplayPort Standard v1.2 and/or PCI Express Standard v1.1, and open-drain current-steering differential outputs compliant to DVI v1.0 and HDMI v1.4b 2 electrical specifications. The I C-bus channel actively buffers as well as level-translates the DDC signals for optimal capacitive isolation. PTN3361C also supports power-saving modes in order to minimize current consumption when no display is active or connected. PTN3361C can be used for either HDMI or DVI level shifting. It provides additional features supporting HDMI dongle detection since support of HDMI dongle detection via the DDC channel is mandatory, the system applications shall enable this feature for correct operation. PTN3361C is powered from a single 3.3 V power supply and is offered in a 32-terminal HVQFN32 package. PTN3361C NXP Semiconductors HDMI/DVI level shifter supporting 1.65 Gbit/s operation MULTI-MODE DISPLAY SOURCE OE N reconfigurable I/Os PCIe PHY ELECTRICAL AC-coupled OUT D4+ TMDS PCIe differential pair OUT D4- output buffer coded TMDS data TX data IN D4+ FF DATA LANE IN D4- TX AC-coupled OUT D3+ TMDS PCIe differential pair OUT D3- output buffer coded TMDS data TX data IN D3+ FF DATA LANE IN D3- TX AC-coupled OUT D2+ PCIe TMDS differential pair OUT D2- output buffer coded TMDS data TX data IN D2+ DATA LANE FF IN D2- DVI/HDMI TX PTN3361C CONNECTOR OUT D1+ AC-coupled PCIe TMDS differential pair OUT D1- clock output buffer clock TX IN D1+ pattern CLOCK LANE FF IN D1- TX 0 V to 3.3 V 0 V to 5 V HPD SOURCE HPD SINK quinary input EQ3 DDC EN 3.3 V (0 V to 3.3 V) 3.3 V 5 V SCL SOURCE SCL SINK 3.3 V 5 V DDC I/O 2 (I C-bus) CONFIGURATION SDA SOURCE SDA SINK DDET aaa-014383 Remark: TMDS clock and data lanes can be assigned arbitrarily and interchangeably to D 4:1 . Fig 1. Typical application system diagram PTN3361C All information provided in this document is subject to legal disclaimers. NXP Semiconductors N.V. 2015. All rights reserved. Product data sheet Rev. 1.1 28 July 2015 2 of 30