SJA1000T/N1,112

INTEGRATED CIRCUITS DATA SHEET SJA1000 Stand-alone CAN controller Product specication 2000 Jan 04 Supersedes data of 1999 Aug 17 File under Integrated Circuits, IC18Philips Semiconductors Product specication Stand-alone CAN controller SJA1000 CONTENTS 6.5.3 Output Control Register (OCR) 6.5.4 Clock Divider Register (CDR) 1 FEATURES 7 LIMITING VALUES 2 GENERAL DESCRIPTION 8 THERMAL CHARACTERISTICS 3 ORDERING INFORMATION 9 DC CHARACTERISTICS 4 BLOCK DIAGRAM 10 AC CHARACTERISTICS 5 PINNING 10.1 AC timing diagrams 6 FUNCTIONAL DESCRIPTION 10.2 Additional AC information 6.1 Description of the CAN controller blocks 11 PACKAGE OUTLINES 6.1.1 Interface Management Logic (IML) 12 SOLDERING 6.1.2 Transmit Buffer (TXB) 12.1 Introduction 6.1.3 Receive Buffer (RXB, RXFIFO) 12.2 DIP 6.1.4 Acceptance Filter (ACF) 12.2.1 Soldering by dipping or by wave 6.1.5 Bit Stream Processor (BSP) 12.2.2 Repairing soldered joints 6.1.6 Bit Timing Logic (BTL) 12.3 SO 6.1.7 Error Management Logic (EML) 12.3.1 Reflow soldering 6.2 Detailed description of the CAN controller 12.3.2 Wave soldering 6.2.1 PCA82C200 compatibility 12.3.3 Repairing soldered joints 6.2.2 Differences between BasicCAN and PeliCAN mode 13 DEFINITIONS 6.3 BasicCAN mode 14 LIFE SUPPORT APPLICATIONS 6.3.1 BasicCAN address layout 6.3.2 Reset values 6.3.3 Control Register (CR) 6.3.4 Command Register (CMR) 6.3.5 Status Register (SR) 6.3.6 Interrupt Register (IR) 6.3.7 Transmit buffer layout 6.3.8 Receive buffer 6.3.9 Acceptance filter 6.4 PeliCAN mode 6.4.1 PeliCAN address layout 6.4.2 Reset values 6.4.3 Mode Register (MOD) 6.4.4 Command Register (CMR) 6.4.5 Status Register (SR) 6.4.6 Interrupt Register (IR) 6.4.7 Interrupt Enable Register (IER) 6.4.8 Arbitration Lost Capture register (ALC) 6.4.9 Error Code Capture register (ECC) 6.4.10 Error Warning Limit Register (EWLR) 6.4.11 RX Error Counter Register (RXERR) 6.4.12 TX Error Counter Register (TXERR) 6.4.13 Transmit buffer 6.4.14 Receive buffer 6.4.15 Acceptance filter 6.4.16 RX Message Counter (RMC) 6.4.17 RX Buffer Start Address register (RBSA) 6.5 Common registers 6.5.1 Bus Timing Register 0 (BTR0) 6.5.2 Bus Timing Register 1 (BTR1) 2000 Jan 04 2