Product Information

TDA19988BHNC1,557

TDA19988BHNC1,557 electronic component of NXP

Datasheet
NXP Semiconductors Video ICs 1.8V I2S HVQFN64

Manufacturer: NXP
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



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0 - Global Stock

MOQ : 1300
Multiples : 1300
1300 : USD 4.0351
N/A

Obsolete
0 - Global Stock

MOQ : 1
Multiples : 1
1 : USD 7.5657
10 : USD 6.6037
100 : USD 5.5703
500 : USD 4.6083
1000 : USD 4.0857
2600 : USD 4.0738
10400 : USD 3.9432
N/A

Obsolete
     
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TDA19988 Low power, 150 MHz pixel rate HDMI 1.4a transmitter with 3 8-bit video inputs, HDCP and CEC support Rev. 3 21 July 2011 Product data sheet 1. General description TDA19988 is a very low power and very small size High-Definition Multimedia Interface (HDMI) 1.4a transmitter. It is backward compatible DVI 1.0 and can be connected to any DVI 1.0 or HDMI sink. This device is primarily intended for mobile applications like Digital Video Camera (DVC), Digital Still Camera (DSC), Portable Multimedia Player (PMP), Mobile Phone and Ultra-Mobile Personal Computer (UM PC), new PC tablet and MID where size and power are key for battery autonomy. This device is also targeting STB HDMI output applications. This part replaces previous TDA9981 Transmitters with increased features and better performances. It allows mixing 3 8-bit RGB or YCbCr video stream at pixel rate up to 165 MHz together 2 with S/PDIF or I S-bus audio streams at audio sampling rate up to 192 kHz. In order to be compatible with most applications, TDA19988 integrates a full programmable input formatter and color space conversion block. The video input formats accepted are YCbCr 4 : 4 : 4 (up to 3 8-bit), YCbCr 4 : 2 : 2 semi-planar (up to 2 12-bit) and YCbCr 4 : 2 : 2 compliant with ITU656 (up to 1 12-bit). In case of ITU656-like format, the input pixel clock can be made active on one (SDR mode) or both edges (DDR mode). TDA19988AHN and TDA19988AET only include a HDCP 1.4 compliant cipher block. The HDCP keys are stored internally in a non-volatile OTP memory for maximum security. This device provides additional embedded features like CEC (Consumer Electronic Control). CEC is a single bidirectional bus that transmits CEC commands (like Standby from remote control) over the home appliance network connected through this bus. This eliminates the need of any additional device to handle this feature thus improving BOM (Bill Of Materials) of the whole system and enabling the connected devices (CEC enabled) to be controlled by only one remote control. TDA19988 supports xvYCC HDMI 1.4a feature. It can be switched to very low power Standby or Sleep modes to save power when HDMI is not used. 2 TDA19988 embeds I C-bus master interface for DDC-bus communication to read EDID and to manage HDCP (TDA19988AHN and TDA19988AET only). 2 This device can be controlled or configured via I C-bus interface.TDA19988 NXP Semiconductors HDMI 1.4a transmitter with HDCP and CEC support PLL 2 I C-BUS SERIALIZER CEC CEC SLAVE PIXEL, REPETITION 2 I S-bus HDMI HMDI HDCP AUDIO ENCODER TMDS S/PDIF 1.4 CIPHER SERIALIZER link video RGB COLOR INPUT 2 SPACE I C-BUS FORMATTER YCbCr MASTER DDC-BUS CONVERTER 001aal264 Fig 1. TDA19988 high-level block diagram 2. Features and benefits Compliance: DVI 1.0 HDMI 1.4a EIA/CEA-861B CEC (HDMI 1.4a) HDCP 1.4 (TDA19988AHN and TDA19988AET only) Video: xvYCC HDMI 1.4a feature Video formats with a pixel rate up to 165 MHz: RGB 4:4:4 YCbCr 4:4:4 YCbCr 4 : 2 : 2 semi-planar YCbCr 4 : 2 : 2 ITU656 3D: Frame Packing: 720p at 50/60 Hz, 1080i at 50/60 Hz, 1080p at 24/30 Hz Side-by-Side (Half): 720p at 50/60 Hz, 1080i at 50/60 Hz, 1080p at 50/60 Hz Top-and-Bottom: 720p at 50/60 Hz, 1080i at 50/60 Hz, 1080p at 50/60 Hz Maximum resolution: 1080p at 50/60 Hz for TV 1600 1200 at 60 Hz for PC (UXGA60) 720p/1080i at 50/60 Hz in ITU656 Programmable color space converter: RGB to YCbCr YCbCr to RGB Programmable input formatter and upsampler/interpolator allow input of any of the 4:4:4, 4:2:2 semi-planar, 4:2:2 ITU656-like formats Horizontal synchronization, vertical synchronization and Data Enable (DE) inputs or VREF, HREF and FREF could be used for input data synchronization 2 In ITU656, pixel clock input can be single or dual edges (selectable by I C-bus) Repetition of video samples as required by HDMI specification Audio: TDA19988 All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved. Product data sheet Rev. 3 21 July 2011 2 of 54

Tariff Desc

8542.31.00 52 No ..CMOS and MOS Microprocessors (MPU), Microcontrollers (MCU) and Digital Signal Processors (DSP)

Electronic integrated circuits: Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
Monolithic integrated circuits Digital.
FR9
Freescale
FREESCALE SEMI
Freescale Semicon
FREESCALE SEMICONDUC
Freescale Semiconductor
Freescale Semiconductor - NXP
NXP
NXP Freescale
NXP (FREESCALE)
NXP / Freescale
NXP SEMI
NXP Semicon
NXP SEMICONDUCTOR
NXP Semiconductors
NXP USA Inc.
PH3
PHI

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