XPC8260VVHFBC NXP

Document Number: MPC8260EC Freescale Semiconductor Rev. 2, 05/2010 Technical Data MPC8260 PowerQUICC II Integrated Communications Processor Hardware Specifications Contents 1. Features 2 This document contains detailed information on power 2. Electrical and Thermal Characteristics 5 considerations, DC/AC electrical characteristics, and AC 3. Clock Configuration Modes . 20 timing specifications for the .29 m (HiP3) devices of the 4. Pinout 23 5. Package Description . 37 PowerQUICC II family of communications processors: the 6. Ordering Information 39 MPC8260 and the MPC8255. Throughout this document, 7. Document Revision History . 39 the MPC8260 and the MPC8255 are collectively referred to as the MPC8260. 2010 Freescale Semiconductor, Inc. All rights reserved.Features Figure 1 shows the block diagram for the MPC8260. 16 Kbytes I-Cache I-MMU System Interface Unit (SIU) 60x Bus G2 Core 16 Kbytes Bus Interface Unit D-Cache 60x-to-Local D-MMU Local Bus Bridge 32 bits, up to 66 MHz Memory Controller Communication Processor Module (CPM) Clock Counter Timers Serial 24 Kbytes Interrupt Dual-Port RAM DMAs Controller System Functions Parallel I/O 32-bit RISC Microcontroller 2 Virtual and Program ROM Baud Rate IDMAs Generators 1 1 2 MCC1 MCC2 FCC1 FCC2 FCC3 SCC1 SCC2 SCC3 SCC4 SMC1 SMC2 SPI I C Time Slot Assigner Serial Interface 2 Non-Multiplexed 3 MII 2 UTOPIA 8 TDM Ports 3 I/O Ports Ports Notes: 1 Not on MPC8255 2 4 on the MPC8255 3 2 on the MPC8255 Figure 1. MPC8260 Block Diagram 1 Features The major features of the MPC8260 are as follows: Dual-issue integer core A core version of the EC603e microprocessor System core microprocessor supporting frequencies of 133200 MHz (150200 MHz for the MPC8255) Separate 16-Kbyte data and instruction caches: Four-way set associative Physically addressed LRU replacement algorithm PowerPC architecture-compliant memory management unit (MMU) MPC8260 PowerQUICC II Integrated Communications Processor Hardware Specifications, Rev. 2 2 Freescale Semiconductor