74AC253, 74ACT253 Dual 4-Input Multiplexer with 3-STATE Outputs
April 2007
74AC253, 74ACT253
tm
Dual 4-Input Multiplexer with 3-STATE Outputs
Features General Description
I and I reduced by 50% The AC/ACT253 is a dual 4-input multiplexer with
CC OZ
3-STATE outputs. It can select two bits of data from four
Multifunction capability
sources using common select inputs. The outputs may
Non inverting 3-STATE outputs
be individually switched to a high impedance state with a
Outputs source/sink 24mA
HIGH on the respective Output Enable (OE) inputs,
ACT253 has TTL-compatible inputs
allowing the outputs to interface directly with bus
oriented systems.
Ordering Information
Order Number Package Package Description
Number
74AC253SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74AC253SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC253PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
74ACT253SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74ACT253SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACT253MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
Device also available Tape and Reel. Specify by appending suffix letter X to the ordering number.
Connection Diagram Pin Descriptions
Pin Names Description
I I Side A Data Inputs
0a 3a
I I Side B Data Inputs
0b 3b
, S Common Select Inputs
S
0 1
Side A Output Enable Input
OE
a
OE Side B Output Enable Input
b
, Z 3-STATE Outputs
Z
a b
FACT is a trademark of Fairchild Semiconductor Corporation.
1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC253, 74ACT253 Rev. 1.574AC253, 74ACT253 Dual 4-Input Multiplexer with 3-STATE Outputs
Logic Diagram Functional Description
The AC/ACT253 contains two identical 4-input multiplex-
ers with 3-STATE outputs. They select two bits from four
sources selected by common Select inputs (S , S ). The
0 1
4-input multiplexers have individual Output Enable (OE ,
a
OE
) inputs which, when HIGH, force the outputs to a
b
high impedance (High Z) state. This device is the logic
implementation of a 2-pole, 4-position switch, where the
position of the switch is determined by the logic levels
supplied to the two select inputs. The logic equations for
the outputs are shown:
Z = OE (I S S + I S S +
a a 0a 1 0 1a 1 0
IEEE/IEC
I
S S + I S S )
2a 1 0 3a 1 0
= OE (I S S + I S S +
Z
b b 0b 1 0 1b 1 0
I
S S + I S S )
2b 1 0 3b 1 0
If the outputs of 3-STATE devices are tied together, all
but one device must be in the high impedance state to
avoid high currents that would exceed the maximum
ratings. Designers should ensure that Output Enable
signals to 3-STATE devices whose outputs are tied
together are designed so that there is no overlap.
Truth Table
Select Inputs Data Inputs Output Enable Outputs
S S I I I I OE Z
0 1 0 1 2 3
XXXXXX H Z
LLL X X X L L
LL H XXX L H
H LXLX X L L
HL XHX X L H
LH X XLX L L
LH X XHX L H
HH XXX L L L
HH XXX H L H
Address Inputs S and S are common to both sections.
0 1
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC253, 74ACT253 Rev. 1.5 2