74AC299, 74ACT299 8-Input Universal Shift/Storage Register with Common Parallel I/O Pins
January 2008
74AC299, 74ACT299
8-Input Universal Shift/Storage Register with Common
Parallel I/O Pins
Features General Description
I and I reduced by 50% The AC/ACT299 is an 8-bit universal shift/storage regis-
CC OZ
ter with 3-STATE outputs. Four modes of operation are
Common parallel I/O for reduced pin count
possible: hold (store), shift left, shift right and load data.
Additional serial inputs and outputs for expansion
The parallel load inputs and flip-flop outputs are multi-
Four operating modes: shift left, shift right, load
plexed to reduce the total number of package pins. Addi-
and store
tional outputs are provided for flip-flops Q , Q to allow
0 7
3-STATE outputs for bus-oriented applications
easy serial cascading. A separate active LOW Master
Outputs source/sink 24mA Reset is used to reset the register.
ACT299 has TTL-compatible inputs
Ordering Information
Package
Order Number Number Package Description
74AC299SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74AC299SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC299MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74AC299PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
74ACT299SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
74ACT299MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74ACT299PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter X to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC299, 74ACT299 Rev. 1.4.074AC299, 74ACT299 8-Input Universal Shift/Storage Register with Common Parallel I/O Pins
Connection Diagram
Logic Symbols
IEEE/IEC
Pin Description
Pin Names Description
CP Clock Pulse Input
DS Serial Data Input for Right Shift
0
DS Serial Data Input for Left Shift
7
S , S Mode Select Inputs
0 1
MR Asynchronous Master Reset
OE , OE 3-STATE Output Enable Inputs
1 2
I/O I/O Parallel Data Inputs or 3-STATE
0 7
Parallel Outputs
Q , Q Serial Outputs
0 7
Functional Description
The AC/ACT299 contains eight edge-triggered D-type
flip-flops and the interstage logic necessary to perform
synchronous shift left, shift right, parallel load and hold
operations. The type of operation is determined by S
0
Truth Table
and S , as shown in the Truth Table. All flip-flop outputs
1
are brought out through 3-STATE buffers to separate I/O
Inputs Response
pins that also serve as data inputs in the parallel load
MR S S CP
1 0
mode. Q and Q are also brought out on other pins for
0 7
expansion in serial shifting of longer words.
LX XX Asynchronous Reset;
Q Q = LOW
0 7
A LOW signal on MR overrides the Select and CP inputs
and resets the flip-flops. All other state changes are initi- HHH Parallel Load; I/O Q
n n
ated by the rising edge of the clock. Inputs can change
HLH Shift Right;
when the clock is in either state provided only that the
DS Q , Q Q , etc.
0 0 0 1
recommended setup and hold times, relative to the rising
HH L Shift Left,
edge of CP, are observed.
DS Q , Q Q , etc.
7 7 7 6
A HIGH signal on either OE or OE disables the
1 2
HL LX Hold
3-STATE buffers and puts the I/O pins in the high imped-
ance state. In this condition the shift, hold, load and reset
H = HIGH Voltage Level
operations can still occur. The 3-STATE buffers are also
L = LOW Voltage Level
disabled by HIGH signals on both S and S in prepara-
0 1
X = Immaterial
tion for a parallel load operation.
= LOW-to-HIGH Transition
1988 Fairchild Semiconductor Corporation www.fairchildsemi.com
74AC299, 74ACT299 Rev. 1.4.0 2