74LVT162245 74LVTH162245 Low Voltage 16-Bit Transceiver with 3-STATE Outputs and 25 Series Resistors in A Port Outputs January 1999 Revised June 2005 74LVT162245 74LVTH162245 Low Voltage 16-Bit Transceiver with 3-STATE Outputs and 25 Series Resistors in A Port Outputs General Description Features The LVT162245 and LVTH162245 contains sixteen non- Input and output interface capability to systems at inverting bidirectional buffers with 3-STATE outputs and is 5V V CC intended for bus oriented applications. The device is byte Bushold data inputs eliminate the need for external pull- controlled. Each byte has separate control inputs which up resistors to hold unused inputs (74LVTH162245), can be shorted together for full 16-bit operation. The T/R also available without bushold feature (74LVT162245). inputs determine the direction of data flow through the Live insertion/extraction permitted device. The OE inputs disable both the A and B ports by Power Up/Down high impedance provides glitch-free placing them in a high impedance state. bus loading The LVT162245 and LVTH162245 are designed with A Port outputs include equivalent series resistance of equivalent 25: series resistance in both the HIGH and 25: making external termination resistors unnecessary LOW states on the A Port outputs. This design reduces line and reducing overshoot and undershoot noise in applications such as memory address drivers, clock drivers, and bus transceivers/transmitters. A Port outputs source/sink r12 mA. B Port outputs source/sink 32 mA/ 64 mA The LVTH162245 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused Functionally compatible with the 74 series 162245 inputs. Latch-up performance exceeds 500 mA These non-inverting transceivers are designed for low volt- ESD performance: age (3.3V) V applications, but with the capability to pro- CC Human-body model 2000V vide a TTL interface to a 5V environment. The LVT162245 Machine model 200V and LVTH162245 are fabricated with an advanced Charged-device model 1000V BiCMOS technology to achieve high speed operation simi- lar to 5V ABT while maintaining a low power dissipation. Also packaged in plastic Fine Pitch Ball Grid Array (FBGA) Ordering Code: Order Number Package Number Package Description 74LVT162245G BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide (Note 1)(Note 2) (Preliminary) 74LVT162245MEA MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide (Note 2) 74LVT162245MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide (Note 2) 74LVTH162245G BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide (Note 1)(Note 2) 74LVTH162245MEA MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide TUBE 74LVTH162245MEX MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide TAPE and REEL 74LVTH162245MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide TUBE 74LVTH162245MTX MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide TAPE and REEL Note 1: Ordering code G indicates Trays. Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code. 2005 Fairchild Semiconductor Corporation DS012446 www.fairchildsemi.comLogic Symbol Connection Diagrams Pin Descriptions Pin Names Description Pin Assignments for SSOP and TSSOP OE Output Enable Input (Active LOW) n T/R Transmit/Receive Input n A A Side A Inputs/3-STATE Outputs 0 15 B B Side B Inputs/3-STATE Outputs 0 15 NC No Connect FBGA Pin Assignments 1 234 56 A B NC T/R OE NC A 0 1 1 0 B B B NC NC A A 2 1 1 2 C B B V V A A 4 3 CC CC 3 4 D B B GND GND A A 6 5 5 6 E B B GND GND A A 8 7 7 8 F B B GND GND A A 10 9 9 10 G B B V V A A 12 11 CC CC 11 12 H B B NC NC A A 14 13 13 14 J B NC T/R OE NC A 15 2 2 15 Truth Tables Inputs Outputs OE T/R 1 1 LL Bus B B Data to Bus A A 0 7 0 7 Pin Assignment for FBGA LH Bus A A Data to Bus B B 0 7 0 7 H X HIGH-Z State on A A , B B 0 7 0 7 Inputs Outputs OE T/R 2 2 LL Bus B B Data to Bus A A 8 15 8 15 LH Bus A A Data to Bus B B 8 15 8 15 H X HIGH-Z State on A A , B B 8 15 8 15 H HIGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance (Top Thru View) www.fairchildsemi.com 2 74LVT162245 74LVTH162245