74VCX08 Low Voltage Quad 2-Input AND Gate with 3.6V Tolerant Inputs and Outputs
December 2013
74VCX08
Low Voltage Quad 2-Input AND Gate with 3.6V Tolerant
Inputs and Outputs
Features General Description
1.2V to 3.6V V supply operation The VCX08 contains four 2-input AND gates. This prod-
CC
uct is designed for low voltage (1.2V to 3.6V) V appli-
3.6V tolerant inputs and outputs CC
cations with I/O compatibility up to 3.6V.
t :
PD
The VCX08 is fabricated with an advanced CMOS
2.8ns max. for 3.0V to 3.6V V
CC
technology to achieve high-speed operation while main-
Power-off high impedance inputs and outputs
taining low CMOS power dissipation.
Static Drive (I /I )
OH OL
24mA @ 3.0V V
CC
Uses proprietary Quiet Series noise/EMI reduction
circuitry
Latchup performance exceeds 300mA
ESD performance:
Human body model > 2000V
Machine model > 250V
Leadless DQFN package
Ordering Information
Package
Order Number Number Package Description
74VCX08M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"
Narrow
(1)
74VCX08BQX MLP14A 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN),
JEDEC MO-241, 2.5 x 3.0mm
74VCX08MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153,
4.4mm Wide
Note:
1. DQFN package available in Tape and Reel only.
Device also available in Tape and Reel. Specify by appending suffix letter X to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
1999 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VCX08 Rev. 1.9.174VCX08 Low Voltage Quad 2-Input AND Gate with 3.6V Tolerant Inputs and Outputs
Connection Diagrams Logic Symbol
Pin Assignments for SOIC and TSSOP IEEE/IEC
Pad Assignments for DQFN
(Bottom View)
(Top View)
Pin Description
Pin Names Description
A , B Inputs
n n
O Outputs
n
DAP No Connect
Note: DAP (Die Attach Pad)
1999 Fairchild Semiconductor Corporation www.fairchildsemi.com
74VCX08 Rev. 1.9.1 2