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This literature is subject to all applicable copyright laws and is not for resale in any manner.74VHC240 Octal Buffer/Line Driver with 3-STATE Outputs April 2007 74VHC240 tm Octal Buffer/Line Driver with 3-STATE Outputs Features General Description High Speed: t = 3.6ns (typ) at T = 25C The VHC240 is an advanced high speed CMOS octal PD A bus buffer fabricated with silicon gate CMOS technology. Low power dissipation: I = 4A (max) T = 25C CC A It achieves high speed operation similar to equivalent High noise immunity: V = V = 28% V (min.) NIH NIL CC Bipolar Schottky TTL while maintaining the CMOS low Power down protection is provided on all inputs power dissipation. The VHC240 is an inverting 3-STATE Low noise: V = 0.9V (max.) OLP buffer having two active-LOW output enables. This Pin and function compatible with 74HC240 device is designed to drive buslines or buffer memory address registers. An input protection circuit ensures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery backup. This circuit prevents device destruction due to mismatched supply and input voltages. Ordering Information Package Order Number Number Package Description 74VHC240M M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74VHC240SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74VHC240MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter X to the ordering number. Pb-Free package per JEDEC J-STD-020B. Connection Diagram Pin Descriptions Pin Names Description OE , OE 3-STATE Output Enable Inputs 1 2 I Inputs I 0 7 O O Outputs 3-STATE Outputs 0 7 1992 Fairchild Semiconductor Corporation www.fairchildsemi.com 74VHC240 Rev. 1.3